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There should be two ways to detect the end of the scanline(or the start of the next scanline): 1. Consecutive detection of two reads on the same PPU address. This requires monitoring all PPU address lines. Here, PPU cycle should be 337-340. After the detection, PPU cycle is at 0. No, this won't wor...

During PPU cycle 1-256, the bg tiles are rendered. Each tile needs to be read four times. A total of four bytes are read in，the first byte is nametable, the second is attribute, the third and fourth are pixel bitmap bytes(8x2bit). Eight PPU cycles are a group, and a row of eight pixels of a tile is ...

There should be two ways to detect the end of the scanline(or the start of the next scanline): 1. Consecutive detection of two reads on the same PPU address. This requires monitoring all PPU address lines. Here, PPU cycle should be 337-340. After the detection, PPU cycle is at 0. 2. Consecutive dete...

Ok, I did further researchs around how MMC5 detects 8x8/8x16 sprites and on which scanline cycles it uses $5120-$5127 and on which $5128-$512B. In order for this, I made a special test case for KrzysioKazzo that simulates CPU/PPU cycles (after each PPU cycle there is CPU cycle so MMC5 never thinks ...

Oh I see what you are saying now. Either it keeps enforcing A13=1, A12=0 and just compares A0-A11, or it only enforces it the first time and then has to compare all 14 bits (which would produce the same function). And you are saying that the former is more likely to be how it is actually implemente...

For ex-attr mode it needs to generate nametable dynamically and switch pattern bank dynamically (with 4K granularity of single screen bg tile). The former needs to cheat ppu_data line, which also needs to redesig the hardware, to add 16 IOs to isolate the bi-directional data bus. That has exceeded ...

Ben Boldt wrote: ↑

Sun Feb 21, 2021 9:21 pm

OK that makes sense lidnariq.

Sorry I hijacked your thread aquasnake, that got away from me a little.

Any detail involved is welcome

The remaining key graphics technologies of mmc5 must be solved to emulate: 1. 8x16 spr mode 2. vsplit mode What's hard about these? We know the MMC5 must keep track of the current sliver # for the scanline, so it can just return (name+pattern table #1) for the first N, (name+pattern table #2) for t...

Mister is equivalent to exposing part of the signal line of PPU to mmc5, but the real cart is different, only through part of the slot interface (ppu_ addr[13:10], /ppu_rd, m2) transmits temporal logic and generates timing. Mister and software emulator can actively synchronize PPU cycle, while the r...

Porting mmc5 PPU cycle counter from mister_nes The NESDEV community has discussed the implementation of scanline detection, in-frame detection and other details. My mmc5 verilog has been able to make some games work properly, such as Metal Slader Glory. For games in 8x16 sprite mode, some can be opp...

When monitoring ppu_data and generate a new ppu_data_out, the data obtained can be placed in reverse order, and the tiles can also be mirrored. The ROM utilization rate of tiles is considerable. 30 years ago, that was definitely a cost-effective technology, but now, nor flash is not a limiting facto...

MicroBankswitcher - 2 byte bank in PRG. What's the intended use of this? The only current use in our project is for using programmer-defined lookup tables. Say, for example, you've generated a table of log for all fixed point values from 00000000.00000000 to 11111111.11111111. The 2-byte microbanks...

The dual 6502 processors, by sharing $6000 - $7fff. The cart carries a noac (umc6561). The two systems run different codes respectively, and shake hands through IRQ. All buses need level shifters for separation.

It looks like the VS system?

Carry a MCU to realize communication transmission such as USB, WiFi, BT, etc. Or use the performance of this MCU to realize multiplication and division. Or use its IO port to realize in-system programming. like these: tpp_main.jpg word-image-16.png FPGA configuration of soft core MCU is not a commer...

The capacitive load on the VCC (+ 5V) path is too large, which leads to slow power down. Monitoring VCC will not effectively shut down SRAM_CE. If the design is a 3.3V system, the monitoring threshold shoud be 3V. You must use LDO to provide an accurate 3.3V voltage, and use a voltage reference sour...