Search found 2 matches

by alphashock
Wed Mar 25, 2020 9:48 am
Forum: NESemdev
Topic: nestest branch instruction address bus
Replies: 2
Views: 175

Re: nestest branch instruction address bus

* If the branch was taken, T2 fetches the byte at PC (what would've been the next opcode) and then adds the previous operand to PCL. If not, it runs T0 for the next instruction. I see. So the address bus still contains PC (original PC + 2 referring to the format above), although the PCL is modified...
by alphashock
Wed Mar 25, 2020 7:44 am
Forum: NESemdev
Topic: nestest branch instruction address bus
Replies: 2
Views: 175

nestest branch instruction address bus

Hi, I'm implementing cycle accurate 6502 CPU emulation. My emulator generates the same output as basic instruction nestest log, although I can see some differences in address/data bus output attached to https://forums.nesdev.com/viewtopic.php?t=13283 nestest bus cycles output C72F A:00 X:00 Y:00 P:2...