Search found 4 matches

by alphashock
Mon Apr 20, 2020 11:22 am
Forum: NESemdev
Topic: branch instruction page cross timing
Replies: 2
Views: 594

Re: branch instruction page cross timing

Oh wow. You are a life saver. Thank you. I searched a little bit and actually 6502.txt gives a good RELATIVE addressing mode explanation: This instruction will check the zero status bit. If it is set, 39 decimal will be subtracted from the program counter and execution continues from that address. I...
by alphashock
Mon Apr 20, 2020 10:31 am
Forum: NESemdev
Topic: branch instruction page cross timing
Replies: 2
Views: 594

branch instruction page cross timing

Hi, I encountered two branch instructions that I think should behave exactly the same with respect to individual cycles, but they are not. Outputs are from sub instruction nestest log. Both instructions test positive, so T2 cycle is executed. BNE @ $C72A C72A A:CB X:04 Y:4F P:6D SP:F1 CPUC:14757 REA...
by alphashock
Wed Mar 25, 2020 9:48 am
Forum: NESemdev
Topic: nestest branch instruction address bus
Replies: 2
Views: 1249

Re: nestest branch instruction address bus

* If the branch was taken, T2 fetches the byte at PC (what would've been the next opcode) and then adds the previous operand to PCL. If not, it runs T0 for the next instruction. I see. So the address bus still contains PC (original PC + 2 referring to the format above), although the PCL is modified...
by alphashock
Wed Mar 25, 2020 7:44 am
Forum: NESemdev
Topic: nestest branch instruction address bus
Replies: 2
Views: 1249

nestest branch instruction address bus

Hi, I'm implementing cycle accurate 6502 CPU emulation. My emulator generates the same output as basic instruction nestest log, although I can see some differences in address/data bus output attached to https://forums.nesdev.com/viewtopic.php?t=13283 nestest bus cycles output C72F A:00 X:00 Y:00 P:2...