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Interesting discoveries. A few questions just to make 100% sure I'm on the same page. Sprite DMA takes 513/514 clocks, depending on whether it's started on an even or odd clock. Would that be 514 clocks if the $4014 write-cycle is on an odd clock, and the usual 513 clocks otherwise? * DMC DMA read n...

Thanks again for your much valuable tests. It seems like the NMI is delayed for another instruction if it's past the point of being able to steal the interrupt from BRK/IRQ, i.e. somewhere around ~5/6 CPU cycles into the ISR. Going with that, I now pass the tests.

It seems like the print functions (print_x, print_y etc.) leaves the PPU rendering ON, causing it to go into its +0/-1 odd-frame-cycle mode. Won't this cause a problem for the sync_nmi routine (it says the rendering should be OFF)? If I disable it manually before sync_nmi is executed, the test passe...

Inside the sync_nmi routine, I noticed that the beq instruction branches directly to cmp and not lda. Was this intentional? I seem to get stuck inside this loop on the very last test since the nmi flag hasn't been set at that point yet. Nice work nevertheless.