nesdev.com

Wow, some interesting questions here. I'm going to answer part of it for now, can't tackle all at once :) First of all, WS1+WS2 should probably be referred to as just "waitstates" or "extra clocks per cycle". The two games set these to 4, and as a result the Cx4 accesses ROM at 4MHz. (20MHz / 5). Th...

Dang, beat me to it. Just commented here: https://github.com/devinacker/bsnes-plu ... -305454286

True, I only fall back to the header location if the header data is found to be unusable (invalid map mode byte). I guess I could add in another little plausibility check to match the map byte against the header location.

HEAD.S specifies Mode 21 (HiROM) but the ROM is only half a bank in size and expects to be loaded from $8000. Try changing db MODE_21 ; D5 - map mode to db MODE_20 ; D5 - map mode in HEAD.S. Edit: still doesn't work, it gets stuck at the white screen... I shall take a closer look.

+1!
Often I find myself pressing "Run", then rapidly switching to the viewport window and jamming the keyboard in a faint hope to deliver a required button press in time. (It's futile of course.)

They do, and for APU RAM, this is the reason the Soul Blader intro tune runs so choppy on some consoles. The player routine reads uninitialized RAM and performs calculations based on it (while it shouldn't). I dumped power-up APU RAM on a number of consoles and listed them here: https://docs.google....

It's two instructions. The RISC is strong with this one.

Oh, good point. I assume you disabled the in-game hooks on the sd2snes for running the tests. Otherwise the hook routine will postpone latching of the PPU H/V counters by about half a scanline (because it hijacks the ISR), enough to make the test fail.

Yes. Basically it stores its wanted and "measured" values in RAM, then does

It sets up various H/V IRQs using $4207-$420a and $4200. The IRQ ISR only reads $2137 once to have the PPU's H/V registers load the count values. It then disables H/V IRQ and waits for VBlank (via NMI ISR setting a flag that is polled in the main loop) to actually do the comparison. The routine to r...

I think they also do an APU RAM test.

@byuu Thanks. Also I recall that on the 1CHIP some (but not all) games that use mid-screen mode changes cause sync glitches where the mode change occurs. I'm guessing(!) that the APU was simply fixed but the rest of the phenomena probably just stem from changes in the analog world where the levels a...

As I've said before, I can't prove it, but my guess is higan is closer to a real SNES than the SNES Jr is. Is there an up-to-date list of the differences? Also to clarify, are you referring to 1CHIP consoles using S-CPUN and S-APU? There are also units using S-CPU, S-PPU1, and S-PPU2 in conjunction...

In that case the IPL ROM should be mapped (unless the SPC700 code changes it later on)

Yeah, thanks to mic_'s SPC->ROM converter and my debugger I was able to figure out why that is (pretty sure it's entirely caused by the IPL ROM being disabled when it shouldn't be) but the mystery is why that's the case to begin with, or why it works on the sd2snes player but not others. Just guess...