Search found 141 matches

by ikari_01
Sun Sep 09, 2018 6:18 pm
Forum: SNESdev
Topic: Some tidbits about the Cx4 (attn: byuu, nocash)
Replies: 47
Views: 50004

Re: Some tidbits about the Cx4 (attn: byuu, nocash)

Wow, some interesting questions here. I'm going to answer part of it for now, can't tackle all at once :) First of all, WS1+WS2 should probably be referred to as just "waitstates" or "extra clocks per cycle". The two games set these to 4, and as a result the Cx4 accesses ROM at 4MHz. (20MHz / 5). Th...
by ikari_01
Sat Apr 29, 2017 11:30 pm
Forum: SNESdev
Topic: Super NES EMULATOR SE dev question
Replies: 32
Views: 9828

Re: Super NES EMULATOR SE dev question

True, I only fall back to the header location if the header data is found to be unusable (invalid map mode byte). I guess I could add in another little plausibility check to match the map byte against the header location.
by ikari_01
Sat Apr 29, 2017 6:37 pm
Forum: SNESdev
Topic: Super NES EMULATOR SE dev question
Replies: 32
Views: 9828

Re: Super NES EMULATOR SE dev question

HEAD.S specifies Mode 21 (HiROM) but the ROM is only half a bank in size and expects to be loaded from $8000. Try changing db MODE_21 ; D5 - map mode to db MODE_20 ; D5 - map mode in HEAD.S. Edit: still doesn't work, it gets stuck at the white screen... I shall take a closer look.
by ikari_01
Thu Dec 15, 2016 1:03 am
Forum: SNESdev
Topic: bsnes-plus and xkas-plus (new debugger and assembler)
Replies: 209
Views: 151593

Re: bsnes-plus and xkas-plus (new debugger and assembler)

+1!
Often I find myself pressing "Run", then rapidly switching to the viewport window and jamming the keyboard in a faint hope to deliver a required button press in time. (It's futile of course.) :lol:
by ikari_01
Sat Dec 10, 2016 7:04 am
Forum: SNESdev
Topic: Looking for CPU<->SMP interface timing test ROM
Replies: 24
Views: 7353

Re: Looking for CPU<->SMP interface timing test ROM

They do, and for APU RAM, this is the reason the Soul Blader intro tune runs so choppy on some consoles. The player routine reads uninitialized RAM and performs calculations based on it (while it shouldn't). I dumped power-up APU RAM on a number of consoles and listed them here: https://docs.google....
by ikari_01
Thu Dec 08, 2016 4:33 pm
Forum: SNESdev
Topic: Fast 2D blitting on Super FX
Replies: 18
Views: 7672

Re: Fast 2D blitting on Super FX

It's two instructions. The RISC is strong with this one.
by ikari_01
Wed Dec 07, 2016 4:38 am
Forum: SNESdev
Topic: SNES Burn-In Test Failure
Replies: 5
Views: 3185

Re: SNES Burn-In Test Failure

Oh, good point. I assume you disabled the in-game hooks on the sd2snes for running the tests. ;) Otherwise the hook routine will postpone latching of the PPU H/V counters by about half a scanline (because it hijacks the ISR), enough to make the test fail.
by ikari_01
Wed Dec 07, 2016 2:19 am
Forum: SNESdev
Topic: SNES Burn-In Test Failure
Replies: 5
Views: 3185

Re: SNES Burn-In Test Failure

Yes. Basically it stores its wanted and "measured" values in RAM, then does

Code: Select all

(m=0)
  lda v_measured
  cmp v_reference
  beq ok
  bra error
ok:
  lda h_measured
  cmp h_reference
  bcc error
[...]
by ikari_01
Wed Dec 07, 2016 2:00 am
Forum: SNESdev
Topic: SNES Burn-In Test Failure
Replies: 5
Views: 3185

Re: SNES Burn-In Test Failure

It sets up various H/V IRQs using $4207-$420a and $4200. The IRQ ISR only reads $2137 once to have the PPU's H/V registers load the count values. It then disables H/V IRQ and waits for VBlank (via NMI ISR setting a flag that is polled in the main loop) to actually do the comparison. The routine to r...
by ikari_01
Tue Dec 06, 2016 9:23 am
Forum: SNESdev
Topic: Looking for CPU<->SMP interface timing test ROM
Replies: 24
Views: 7353

Re: Looking for CPU<->SMP interface timing test ROM

I think they also do an APU RAM test.
by ikari_01
Mon Dec 05, 2016 10:01 am
Forum: SNESdev
Topic: Interest in "modern" SNES Development Hardware?
Replies: 153
Views: 34369

Re: Interest in "modern" SNES Development Hardware?

@byuu Thanks. Also I recall that on the 1CHIP some (but not all) games that use mid-screen mode changes cause sync glitches where the mode change occurs. I'm guessing(!) that the APU was simply fixed but the rest of the phenomena probably just stem from changes in the analog world where the levels a...
by ikari_01
Mon Dec 05, 2016 8:36 am
Forum: SNESdev
Topic: Interest in "modern" SNES Development Hardware?
Replies: 153
Views: 34369

Re: Interest in "modern" SNES Development Hardware?

As I've said before, I can't prove it, but my guess is higan is closer to a real SNES than the SNES Jr is. Is there an up-to-date list of the differences? Also to clarify, are you referring to 1CHIP consoles using S-CPUN and S-APU? There are also units using S-CPU, S-PPU1, and S-PPU2 in conjunction...
by ikari_01
Tue Nov 08, 2016 12:18 pm
Forum: SNESdev
Topic: SPC File Format looks like S***
Replies: 50
Views: 15537

Re: SPC File Format looks like S***

In that case the IPL ROM should be mapped (unless the SPC700 code changes it later on)
by ikari_01
Tue Nov 08, 2016 9:23 am
Forum: SNESdev
Topic: SPC File Format looks like S***
Replies: 50
Views: 15537

Re: SPC File Format looks like S***

Yeah, thanks to mic_'s SPC->ROM converter and my debugger I was able to figure out why that is (pretty sure it's entirely caused by the IPL ROM being disabled when it shouldn't be) but the mystery is why that's the case to begin with, or why it works on the sd2snes player but not others. Just guess...