Search found 652 matches

by krzysiobal
Fri Feb 28, 2020 3:21 pm
Forum: NES Hardware and Flash Equipment
Topic: CSM04048N Speech chip
Replies: 1
Views: 53

Re: CSM04048N Speech chip

Looks like one of the companies in my country has this chip as well as similar ones (CSM04049N, CSM04054N). I asked them for availability & price, so maybe eventual tests/decapping could be done without destroying the original cartridge, just first need to figure out the pinout.
by krzysiobal
Thu Feb 27, 2020 6:53 am
Forum: NES Hardware and Flash Equipment
Topic: Schematic for UM6561?
Replies: 30
Views: 19589

Re: Schematic for UM6561?

Nice wake-up after 2.5 years of inactivity, where have you been for that whole period of time?
by krzysiobal
Wed Feb 26, 2020 9:25 am
Forum: NES Hardware and Flash Equipment
Topic: Building a 0 chip cartridge
Replies: 3
Views: 311

Building a 0 chip cartridge

I have an evil and completely useless idea (just a proof of concept that this can be done) of making a cartridge that has 0 chips, only discrete elements (like resistors, diodes, probably transistors will be needed to). Let's assume that the "project" will be run on Famicom (or oter 100% compatible ...
by krzysiobal
Sat Feb 22, 2020 5:52 pm
Forum: NES Hardware and Flash Equipment
Topic: Aladdin Deck Enhancer / CCU_v2.00 CF30288 pinouts
Replies: 2
Views: 309

Aladdin Deck Enhancer / CCU_v2.00 CF30288 pinouts

Basing on the only existing photos of Aladdin Deck Enhancer v1.1 I tried to reverse engineer the pinout of cartridge connector as well as CCU_v2.00 CF30288 chip (which should be equivalent in functin to the BF909X chip found in single cartridges) The CIC stun circuit is the same like kevtris describ...
by krzysiobal
Fri Feb 21, 2020 7:13 pm
Forum: NES Hardware and Flash Equipment
Topic: Irem's TAM-S1 IC analysis
Replies: 11
Views: 690

Re: Irem's TAM-S1 IC analysis

So a rising edge of pin 19 will end the write condition. Will a rising edge of pin 9? Pin 28? Falling edge of pin 8? In other words, are the other signals part of the equation that generates the clock to the register, or does the register have a clock enable? Only rising edge of pin 19 makes write ...
by krzysiobal
Fri Feb 21, 2020 6:38 pm
Forum: NES Hardware and Flash Equipment
Topic: Irem's TAM-S1 IC analysis
Replies: 11
Views: 690

Re: Irem's TAM-S1 IC analysis

Are PRGA14...PRGA18 just the latched value OR (pin 8 XOR pin 28) Yes what disables the ROM, but you also found that it was a rising edge of pin 19 when pin6=0 No, no.. I just wanted to point that latching occurs on edge, not on level. On the rising edge of pin 19 chip checks for proper values of ot...
by krzysiobal
Fri Feb 21, 2020 6:23 pm
Forum: NES Hardware and Flash Equipment
Topic: Irem H3001 - pinout
Replies: 0
Views: 257

Irem H3001 - pinout

Used in games: * Spartan X 2, * Daiku no Gen-san 2: Akage no Dan no Gyakushuu, * Kaiketsu Yanchamaru 3: Taiketsu! Zouringen, * Ai Sensei no Oshiete: Watashi no Hoshi This time unfortunatelly only basing on the images of Spartan X2 . For furter testing need to wait if one of the above games gets chea...
by krzysiobal
Thu Feb 20, 2020 6:54 pm
Forum: NES Hardware and Flash Equipment
Topic: Irem's TAM-S1 IC analysis
Replies: 11
Views: 690

Re: Irem's TAM-S1 IC analysis

I checked if there seems to be other registers, by issuing a write of different value at the second bank address, also reading with different values of Pin22/23 and it does not affect the currently described functionality - everything seems to be the same (PRG banking, mirroring, data in/data out pi...
by krzysiobal
Thu Feb 20, 2020 9:31 am
Forum: NES Hardware and Flash Equipment
Topic: Irem's TAM-S1 IC analysis
Replies: 11
Views: 690

Re: Irem's TAM-S1 IC analysis

Hm. In that case, why did you guess that pin 17 was D5 and not D6?
Can be D6 aswell or even any address bit :)
Because the current mapper definition assigns D6 and D7 to mirroring control and this bit without additional wires does not have influence to mirroring, I prefered to not use it.
by krzysiobal
Thu Feb 20, 2020 9:26 am
Forum: NES Hardware and Flash Equipment
Topic: Family Trainer 3: Aerobics Studio - Mitsubishi M50805
Replies: 18
Views: 16407

Re: Family Trainer 3: Aerobics Studio - Mitsubishi M50805

I reverse engineered the PCB in case someone is interested:
sch.png
pcb-light-names.jpg
pcb-components.jpg
pcb-bottom.jpg
There are protection diodes that would make dumping using "Kazzo-thing" harder.
by krzysiobal
Wed Feb 19, 2020 12:40 pm
Forum: NES Hardware and Flash Equipment
Topic: Irem's TAM-S1 IC analysis
Replies: 11
Views: 690

Re: Irem's TAM-S1 IC analysis

... so in conclusion, it does have bus conflicts, for absolutely no good reason? In the first half of PRG space (where the register is located) - no bus conflicts. But the other one suffers from bus conflicts. Don't see good reason what's the point of enablin ROM there. Maybe the line can be reused...
by krzysiobal
Tue Feb 18, 2020 6:20 pm
Forum: NES Hardware and Flash Equipment
Topic: Irem's TAM-S1 IC analysis
Replies: 11
Views: 690

Irem's TAM-S1 IC analysis

I'm checking the TAM-S1 chip. Apparently, `Kaiketsu Yanchamaru` (256kB PRG / 8kB CHR-RAM) is the only game that uses it. Mapper 97 is extremelly simple, but this 28 pin mapper chip seems to be connected in extraweird way - lot of not connected pins, multpiple +5Vs/GNDs. After desoldering it I was ab...
by krzysiobal
Tue Feb 18, 2020 2:33 pm
Forum: NES Hardware and Flash Equipment
Topic: Sunsoft 3 testing
Replies: 7
Views: 674

Re: Sunsoft 3 testing

None of them is used to assert PRG /CE - they can be both 0. Just /ROMSEL and R/W are taken into account.
by krzysiobal
Tue Feb 18, 2020 2:32 pm
Forum: Reproduction
Topic: Akira TC0190 questions
Replies: 11
Views: 3287

Re: Akira TC0190 questions

Pin 31 is the true GND in that chip because a bold track goes to it. The track from pin 20 goes to a via and then out of the board (probably for gold-plating) and nowhere else. But after desoldering pins 20 and 31 I can confirm that they are connected internally inside chip so both are GNDs. Pins 35...
by krzysiobal
Tue Feb 18, 2020 12:42 pm
Forum: NES Hardware and Flash Equipment
Topic: Sunsoft 3 testing
Replies: 7
Views: 674

Re: Sunsoft 3 testing

Sounds like pin 1 and pin 2 are actually used together to act as the enable to the ASIC, and the two are ANDed together... When pin1 is tied to VCC and pin2 to the M2, IRQ counter does not decrease (but RAM/Registers works). So probably IRQ counter is clocked by edge on pin 1 and also pin 2 need to...