Search found 11 matches

by Elessar
Fri Mar 09, 2012 2:56 pm
Forum: NESemdev
Topic: PPU Nametables
Replies: 34
Views: 10833

I will start implementing mirroring now, but that should not be causing the glitches. I have verified that all the PPU memory accesses have stayed within the $2000 nametable, and the nametable viewer I wrote displays the nametable perfectly. EDIT: I implemented mirroring, but the glitches still rema...
by Elessar
Fri Mar 09, 2012 9:38 am
Forum: NESemdev
Topic: PPU Nametables
Replies: 34
Views: 10833

It looks like I had overlooked two essential items: NMI & DMA. Here is what the system looks like now: http://img853.imageshack.us/img853/989/donkeykongingame1.png http://img201.imageshack.us/img201/9864/donkeykongingame2.png As you can see, the left side and some of the top is not showing correctly...
by Elessar
Fri Feb 24, 2012 12:51 pm
Forum: NESemdev
Topic: PPU Nametables
Replies: 34
Views: 10833

I realized that the tile set preview wasn't reading the bytes correctly. Here is a screenshot of the game running with the tile sets and name tables:

Image
by Elessar
Wed Feb 22, 2012 1:25 pm
Forum: NESemdev
Topic: PPU Nametables
Replies: 34
Views: 10833

Yes, the game is running (the debugger runs through the code).
It would also help if you had actual tile graphics showing.
Do you mean the tile sets? Here they are:
Image

I apologize if I misunderstood you, it's been a long day.
by Elessar
Wed Feb 22, 2012 12:00 pm
Forum: NESemdev
Topic: PPU Nametables
Replies: 34
Views: 10833

PPU Nametables

I am in the process of implementing the PPU, but I am having problems trying to get the nametables to load properly. Here is a comparison of nametables for Donkey Kong on my emulator & FCEUXDSP. http://img688.imageshack.us/img688/6716/donkeykongnametables.png Would this be a result of improper initi...
by Elessar
Tue Oct 25, 2011 7:56 pm
Forum: NESemdev
Topic: Cycle bug in CPU
Replies: 2
Views: 1841

You hit the nail on the head!

Like most small mistakes, it seems so obvious now. Thank you very much! :)
by Elessar
Mon Oct 24, 2011 9:37 pm
Forum: NESemdev
Topic: Cycle bug in CPU
Replies: 2
Views: 1841

Cycle bug in CPU

In order to insure that all the opcodes execute correctly in my CPU, I have been using the nestest ROM along with its corresponding log . Although the instructions execute properly, there is a problem that I have with the BEQ opcode, 0xF0. Here are the results according to nestest: CFFE F0 05 BEQ $D...
by Elessar
Sun Oct 16, 2011 4:36 pm
Forum: NESemdev
Topic: PPUSTATUS lower bits
Replies: 8
Views: 2492

Yes, you can ignore D4-D0 of PPUSTATUS because games typically use instructions that likewise ignore these bits. Good to know. 1. How many bits are written to PPUSTATUS as a result of data being written into a PPU register - 4 bits or 5 bits? I'm not aware of any test ROM for PPU open bus behavior,...
by Elessar
Sun Oct 16, 2011 4:08 pm
Forum: NESemdev
Topic: PPUSTATUS lower bits
Replies: 8
Views: 2492

Re: PPUSTATUS lower bits

However, the Nestech document provides this information NESTECH.txt is very old. ... 2. Is bit 4 actually a VRAM write flag? No. I suspected that this might be the case, but I wanted to make sure. 1. How many bits are written to PPUSTATUS as a result of data being written into a PPU register - 4 bi...
by Elessar
Sun Oct 16, 2011 3:50 pm
Forum: NESemdev
Topic: PPUSTATUS lower bits
Replies: 8
Views: 2492

PPUSTATUS lower bits

I'm in the middle of my PPU development, and I would like to clear up a few things about the PPUSTATUS register. Most of the sources of information that I have checked so far more or less agree with what is said in the wiki: 76543210 |||||||| |||+++++- Least significant bits previously written into ...
by Elessar
Tue Jun 14, 2011 6:58 pm
Forum: NESemdev
Topic: PPU memory mirroring
Replies: 2
Views: 3063

PPU memory mirroring

Hi, I am writing a NES emulator for fun, and I have already have the CPU executing all the instructions correctly according to nestest.nes. Now I am starting to write the PPU, but I find the memory map somewhat confusing. According to NinTech and other documents, the memory map for the PPU is more o...