Search found 48 matches

by gekkio
Sat Jul 27, 2019 2:23 am
Forum: GBDev
Topic: First homebrew cart attempt
Replies: 16
Views: 13141

Re: First homebrew cart attempt

A0-A15 -> A0-A15 (obviously) CE -> CS (Pin 5 of edge connector) This doesn't look right to me. Cartridge connector ~CS is not a chip select signal for a ROM , and if you use it like that, you can cause hardware damage because there will be bus contention with the work RAM chip. But since you haven'...
by gekkio
Mon Jan 28, 2019 2:08 pm
Forum: GBDev
Topic: Game Boy CPU isn't a Z80. What is it?
Replies: 17
Views: 17042

Re: Game Boy CPU isn't a Z80. What is it?

nitro2k01 wrote:Have you documented the details of this publicly anywhere?
Do you mean the NMI stuff? Not yet, because I haven't researched it...I just know there's an NMI pin because I've seen the test point on CGB boards.
by gekkio
Tue Jan 22, 2019 12:01 pm
Forum: GBDev
Topic: Game Boy CPU isn't a Z80. What is it?
Replies: 17
Views: 17042

Re: Game Boy CPU isn't a Z80. What is it?

Let's take a look at various facts... SM8311/13/14/15 (Sharp Microcomputer Data Book 1996) : * Sharp SM8311/SM8313/SM8314/SM8315 are 8-bit "microcomputers" intended for home appliances * They use a SM83 CPU core * They use a CPU register set and an instruction set that is a 100% match with the Game ...
by gekkio
Thu Jun 21, 2018 6:37 am
Forum: GBDev
Topic: Verilog MBC5
Replies: 14
Views: 11204

Re: Verilog MBC5

... Wait, what? How does that happen? There's a couple of possible scenarios, but to be fair, using A[15..13] wouldn't probably lead to any actually bad thing. It's more about principles: there's a chip select signal (CS or A15 depending on the memory area), and when it's high, you're not supposed ...
by gekkio
Tue Jun 19, 2018 12:21 am
Forum: GBDev
Topic: Verilog MBC5
Replies: 14
Views: 11204

Re: Verilog MBC5

... also, those linked timing graphs are subtly different from their graphs in their Complete Technical Reference. Yeah, trust GBCTR in this case ;) The difference is naming (CS vs MREQ) and in GBCTR the graphs continue for one more clock edge to illustrate the fact that some signals are deasserted...
by gekkio
Wed Dec 06, 2017 7:15 am
Forum: GBDev
Topic: Naughtyemu, what is it doing? [solved]
Replies: 4
Views: 2912

Re: Naughtyemu, what is it doing?

I published the sources here: https://github.com/Gekkio/naughtyemu The basic idea involves OAM DMA and HALT. If OAM DMA is running when HALT is entered, the OAM DMA is suspended but ends up leaving some internal bus in a busy state. If HALT is eventually exited, OAM DMA continues from where it stopp...
by gekkio
Wed Dec 06, 2017 3:57 am
Forum: GBDev
Topic: Naughtyemu, what is it doing? [solved]
Replies: 4
Views: 2912

Re: Naughtyemu, what is it doing?

It's a silly test ROM I made two years ago around christmas time 8-) It tests certain special behaviour that no emulator gets right. On real hardware you get just a blank screen instead of the text you saw. However, this test ROM doesn't fully test that behaviour so some emulators end up with the bl...
by gekkio
Tue Oct 31, 2017 8:21 am
Forum: GBDev
Topic: Gameboy CPU instruction set timings and lengths
Replies: 12
Views: 4664

Re: Gameboy CPU instruction set timings and lengths

Are any games actually affected by a lack of "fine-grained timing"? Yes, but only like 5%-10% so you can get very far without worrying about this kind of stuff. And the important bits involve mostly other things than the CPU. Is there a microcode reference that I can use to improve the timings? I.e...
by gekkio
Tue Oct 31, 2017 5:16 am
Forum: GBDev
Topic: Gameboy CPU instruction set timings and lengths
Replies: 12
Views: 4664

Re: Gameboy CPU instruction set timings and lengths

If you want to also pass my test ROMs at some point, you'll need fine-grained timing. :twisted:
...I'm just going to leave this here: https://github.com/Gekkio/mooneye-gb#ac ... comparison
by gekkio
Wed Sep 20, 2017 10:46 am
Forum: GBDev
Topic: Verilog implementation problems
Replies: 10
Views: 3862

Re: Verilog implementation problems

It's S29GL032 and it's on a DE1 board, and I don't believe speed to be the issue honestly. Yes, it is NOT a 5V tolerant dev board at the moment. Cyclone II seems to have a maximum rating of 4.6 V on the IO pins, so this doesn't seem like a great idea to do with a $150 dev board. I wouldn't be surpr...
by gekkio
Tue Sep 19, 2017 10:08 pm
Forum: GBDev
Topic: Verilog implementation problems
Replies: 10
Views: 3862

Re: Verilog implementation problems

What kind of flash are you using? I don't see any immediate problems with the code, but the speed and expected memory timings of the flash could be a cause for problems so a datasheet would be helpful.

Also, I'm curious: which Altera dev board are you using that is 5V tolerant?
by gekkio
Wed Aug 30, 2017 12:48 pm
Forum: GBDev
Topic: DMA Transfer - 160 microseconds?
Replies: 16
Views: 13226

Re: DMA Transfer - 160 microseconds?

So the first instruction, the CPU actually reads (FF) in 1 cycle, then it reads the remaning in the other 3 cycles. After that it does the FF thing again, then do the load for 3 cycles? I think you're mixing T-cycles and M-cycles. In this screenshot CLK = T-cycles, PHI = M-cycles. None of the instr...
by gekkio
Wed Aug 30, 2017 12:44 pm
Forum: GBDev
Topic: DMA Transfer - 160 microseconds?
Replies: 16
Views: 13226

Re: DMA Transfer - 160 microseconds?

And that part i get, but was wondering about the Timer and Interruption. Those are updated on a per instruction basis right? Timer (TIMA) works at M-cycle granularity (not at instruction granularity!). The real interrupt sources in the system work at various granularities all the way down to half T...
by gekkio
Wed Aug 30, 2017 12:27 pm
Forum: GBDev
Topic: DMA Transfer - 160 microseconds?
Replies: 16
Views: 13226

Re: DMA Transfer - 160 microseconds?

I just chose the numbers to reflect the relative machine cycle position compared to the "first OAM DMA cycle". Here's a real hardware trace of a case almost identical to the one posted earlier: https://gekkio.fi/files/rubbish/oam_dma.png The CPU is running these instructions: $0150: LD A, $40 $0151:...
by gekkio
Wed Aug 30, 2017 10:06 am
Forum: GBDev
Topic: DMA Transfer - 160 microseconds?
Replies: 16
Views: 13226

Re: DMA Transfer - 160 microseconds?

It's even more confusing when you consider the fact that the total duration is actually 161 machine cycles if you count from the DMA register write ;) (at least on DMG/SGB/MGB/SGB2). When OAM DMA is started, there is one machine cycle delay before the actual transfer starts. So, let's say you start ...