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100 cycles is the maximum number for which the chip is still guaranteed to retain data for the full rated number of years and across the full temperature and voltage range. Some years ago, someone sold a bunch of kits to intentionally wear out a small serial EEPROM . Subsequent reports showed that ...

Probably worth taking the time to play through those games again on an emulator or better cart. If you have lost lots of progress, you could google up cheat codes or Game Genie codes to get back to where you were more quickly. Also, you can find SRAM and freeze state files online too. That will prob...

Honestly you should throw that cartridge in the garbage can. It may damage a real Famicom due to incorrect logic levels. I have 2 different 143-in-1 carts, neither identical to yours. Both of mine only have 8k save RAM total, so any time you play a different game, it overwrites the save of the previ...

And what a lot of older emulators didn't emulate is that if I remember correctly, the N163's volume control fades toward 8, not 0. Given that there are 15 volume levels and 15 M2 cycles per full cycle of the N163 WSG, my pet theory is that it uses the volume register to control a pulse width modula...

I haven't had a habit of testing emulators for audio accuracy, so I don't really know who gets N163 right I didn't test many myself either, just a few. Confirming that Mesen is better than FCEUx at keeping the waveform centered. I have not tested samples longer than 32 on Mesen. FCEUX: n163_FCEUX.p...

I have never seen ANYTHING other than a real Namco-163 chip that supports this. I think this is partially because our Wiki needs refinement. No, the source of that misunderstanding is Goroh's document from 1997, which many older emulators based their implementation on. The wiki has been quite clear...

N163: Wave sizes past 32 aren't supported. I have never seen ANYTHING other than a real Namco-163 chip that supports this. I think this is partially because our Wiki needs refinement. Also, I have noticed that, just looking visually at the sound wave produced in 4-channel mode, the real Namco-163 i...

I don't have it, sorry. I just sent an email to the hotmail address on the software page with the images attached and they created the Hello Kitty World profile for me... Maybe they could help? It seems you have to log in to get to that email link. Send me a PM if you want the email address directly.

Just noticed this thread -- attaching photos of my PCB.

I just have to chime in and say that you guys are completely crazy.

It looks like the chips should be facing toward you when you insert it. Putting it in the wrong way might cause damage. Try what krzysiobal said to clean it. If that still does not work, you can use an old toothbrush with some liquid soap and scrub the entire board, adding small amount of water peri...

A couple updates. Transitioning to reset inactive state does not care about PA12. I came up with no simulation where checking PA12 for this made any difference. However, this transition does have to be on falling edge M2. It could be possible to rearrange things or change dependencies in such a way ...

You know it's getting good when I fire up Visio, I no longer know of a test condition that fails: scanline_states.png 4-Bit counter (M2 falling edge): (Basically: In sprite state, counts to 15 clocks before switching to background state on the 16th clock.) INC if "Sprite" && (4-bit != 15) && (PA12 =...

Diagram updates. I was able to correct a corner case I found in the sprite-to-background transition. The chip must be checking PA12=0 to make this transition. Normally, the 4-bit counter requires PA12 = 0 in order to increment. So, PA12 must remain 0 for 15 cycles to make the 4-bit counter = 15. The...

I found today that the power-on-reset value of C000 appears to always be FF, I have found no exception to this. If I just totally skip writing to C000 (i.e. replace it with a dummy read in my test), I will get an IRQ at the 256th scanline detected, and looping naturally, I get another IRQ at 512th s...