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Just to let y'all know, during my testing with Holy Mapperel on my SxROM boards, I encountered a problem - the "detailed test" result was coming back as 0x1000, which corresponds to an issue with enabling/disabling the PRG RAM. As it turns out, the AX5904 is based on MMC1A, which has PRG RAM always ...

No problem! Good luck!
(Labels are the worst part lol)

I use 13A, but they're nearly identical with a few inconsequential changes.

Check out this forum thread:

http://forums.nesdev.com/viewtopic.php? ... 7&start=15

The only barrier to entry is a programmer that can program the ATtiny13. I use a GQ-4x4 but that's at least $100.

nocash wrote: ↑

Sun Feb 21, 2021 11:16 am

Yes, the note under the table on http://problemkaputt.de/fullsnes.htm#sn ... tsmadchips does say just that:
"when using two ROMs, Addr2 is used as upper ROM address line (eg. Addr2=A20 for a cart with two 1Mbyte ROM chips)"

Wow I'm a big ol' dummy lol
Thanks.

tepples wrote: ↑

Thu Jan 24, 2019 8:32 am

How I interpret Game Pak slot pin descriptions from Fullsnes:

This is a question for dual-ROM boards, but

On this site, for the MAD-1 pin descriptions, it has pin 13 (Addr2) connected to A21. Shouldn't it be connected to A20 for SHVC-2XXX boards? (Two 8 Mbit ROMs)

Yeah, that could work. I'd personally put the bank bits adjacent: it makes the programming a little cleaner. I think I'd be tempted to avoid the 9th PRG bank bit just to avoid needing another OR gate.... well, that and low availability of 5V flash bigger than 2MB. Yeah, just a quick sketch, it'd pr...

lidnariq wrote: ↑

Sun Feb 14, 2021 1:33 pm

I'd probably personally go for the "use the address bus" version of the design, but it's up to you.

Like this?
Theoretical 8MB PRG with 128KB CHR (use a 1008 series SRAM)
(This would also require another set of OR gates, but you could exclude A11-A13 for smaller space)

Thanks as always for the insight. Definitely gonna look into those CPLDs at some point, when time allows

Yeah after I posted that and started thinking more about it, I realized the issue with using D0-D2 like that. I don't think the bus conflict prevention is a great way to go about this. And adding multiplexers is equally clunky. And thank you for the insight. I don't think the goal is to create a new...

If they're using mapper 30, it means nesmaker, which means they aren't going to be manually programming and expect it to be nesmaker compatible. Nah he's not using NES Maker. You can still make a Mapper 30 compatible game without it, though I'm not sure how exactly he's going about making the game....

The 512KB design limit ultimately comes from the price increase from the 512KB SST39SF040 to larger ROMs. Micron had discontinued their M29F parts about six years ago, and only Macronix provided 1MB 5V NOR flash and that at a mediocre price. So larger ROMs required 3V translation and that added eno...

I'm helping someone out with a game they're making, and they'd like to have a board with more ROM space on it than Mapper 30's 512KB. Has anyone done a modification to Mapper 30 to expand the space available? They need to keep the same amount of CHR available as well as the dynamic mirroring control...

I don't know if or how the gates need to be connected to the battery. Using a 62256 to do this is tricky, because you only have one enable pin to work with - the added logic makes it complicated to wire up. I have found that logic devices allow a small but significant leakage current through the ou...

What I'm trying to get at is you can't put two 32 Mbit games on one 32 Mbit EPROM.
So how can you store two 64 Kbit saves on one 64 Kbit SRAM chip?