Search found 32 matches

by srg320
Sun Apr 07, 2019 5:16 am
Forum: SNESdev
Topic: Mesen-S - SNES Emulator
Replies: 370
Views: 180703

Re: Mesen-S - SNES Emulator

Alien Vs Predator There are 2 V-IRQ interrupts by frame: 16 and 209 scanlines. On line 209 every first IRQ handler is ending on line ~210. On line 225 run NMI handler. Снимок.PNG On line 209 every second IRQ handler is ending on line ~238-245 (i.e. in VBlank), NMI handler does not start and one fram...
by srg320
Thu Apr 04, 2019 8:39 am
Forum: SNESdev
Topic: Mesen-S - SNES Emulator
Replies: 370
Views: 180703

Re: Mesen-S - SNES Emulator

I checked Mesen-S on my problem games and some games have the same issues that I had on my FPGA SNES :) . 1. Wild Guns, flickering TSB $66 must be executed before runs NMI handler. Снимок.PNG https://board.zsnes.com/phpBB3/viewtopic.php?p=77276&sid=bf8f0333cabdc554baa99bf8b3946eb4#p77276 2. Robo Cop...
by srg320
Tue Feb 12, 2019 10:16 am
Forum: SNESdev
Topic: Internal OAM address sprite evaluation
Replies: 17
Views: 15195

Re: Internal OAM address sprite evaluation

Found interesting information about Uniracers.
I made a temporary patch PPU and now Uniracers works well, but need rework sprites engine for correct work.
by srg320
Wed Oct 03, 2018 10:31 pm
Forum: SNESdev
Topic: Window color gradient with hdma?
Replies: 8
Views: 5242

Re: Window color gradient with hdma?

There are some examples of gradient (RedSpace...) and window with source codes.
by srg320
Sun Aug 19, 2018 1:29 am
Forum: SNESdev
Topic: More detail on SNES PPU tile-to-pixel pipeline/compositing?
Replies: 3
Views: 4465

Re: More detail on SNES PPU tile-to-pixel pipeline/compositi

tepples wrote:This priority encoder is double-pumped, meaning it can return two results per pixel
Mode 7 also uses double-pumped for get two results of the multiplication or uses two separate multipliers?

Thanks, very helpful information.
by srg320
Fri Aug 03, 2018 2:40 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

magno wrote:Because some instruction have an Internal Operation cycle whilst RWB is '1', so CPU_RD would go low even if no read cycle is executing.
To determine Internal Operation cycle I use VDA and VPA, maybe it wrong.
by srg320
Fri Aug 03, 2018 2:17 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

magno wrote:tDECOD is combinational propagation delay to decode CPU_RD from full address (bank + offset) and RWB signal.
Why do you think that CPU_RD is decoded from address and not just RWB? I think it something like ~(RWB & PHI2).
by srg320
Thu Aug 02, 2018 9:40 pm
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

According to the logical analyzer traces from this post (LISTING8.txt) CPU_RD/CPU_WR is 3/3 and 3/5 master cycles long when work CPU and 4/4 when work DMA.
by srg320
Thu Aug 02, 2018 12:18 pm
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

I read all this information in the W65C816S datasheet from Western Digital (year 2010); table 4-2 has the timings for 5Vcc (even if the column say "14MHz", those timings apply because they are related to Vcc, not the maximum frequency). Figure 5-1 shows the bank latching circuit, the one I think SN...
by srg320
Thu Aug 02, 2018 11:15 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

Thanks magno, you are the only one who gives very useful information. I have little experience in this. Address bank appears on data bus at most 33ns after PHI2 falling edge (your signals are rising-edge-aligned, but I think the correct is falling-edge as in PHI2). This byte is latched and after lat...
by srg320
Thu Aug 02, 2018 7:24 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

tepples wrote:Could the S-DD1 be prefetching the PHA during the $4801 write cycle and the PLA during the "internal operation" cycles of PHA?
SFA2 instead PHA PLA uses:

Code: Select all

STA $00
STA $00
and

Code: Select all

LDY $00
LDY $00
by srg320
Thu Aug 02, 2018 6:51 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

Can so you will understand that I mean
Документ1.png
by srg320
Thu Aug 02, 2018 4:45 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

How did you resolve finally SNES CPU / SDD1 core collision after writing to $4801? SDD1 accesses ROM when both CPURD and CPUWR in high level, it takes 3 master cycles always . Thus, one CPU cycle is one ROM reading for SDD1. After writing to $4801 and before starting DMA are 9-10 CPU cycles. I use ...
by srg320
Wed Aug 01, 2018 4:16 am
Forum: SNESdev
Topic: SDD1 FGPA implementation
Replies: 58
Views: 37383

Re: SDD1 FGPA implementation

Great!! It would be nice there were some open-sorce projects for SNES FPGA implementation. It could be use for homebrew, getting the most of SNES system, adding features... In the future I want to do something like hardware debugger via USB. Scheme of my board is applied. Maybe there is something I...