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Alright, so most of the lines that go to the output unit turned out to be instrument information anyway. Each control line seems to extract different information on the instruments. How the information is arranged in the bytes sent out is somewhat different from how it is when writing bytes to the c...

Assuming that I didn't make any mistakes, here should be all the conditions to enable certain control lines in the data output selecting circuit, as well as have the /CPU out line low. I'm not yet sure of what each one of these lines do. According to the wiki some of the pins change their function i...

Probably a very complicated question, but those 3 extra patches are drum patches. Nobody is aware of any way to use them, our assumption is that they are just an artifact left in there from the YM2413. However the last byte of the SD/HH patch is different than the YM2413 which is very curious. Any ...

Can you tell, is pin #48 actually not connected internally (per out wiki's pinout)? If it is connected to something, does it by any chance look similar to pin #43 (audio output)? The pin is connected. It seems to be a NOR between pin #01 (PPU /RD) and pin #02 (PPU A13). The 13th address bit seems t...

While looking at the die shot of VRC7 I noticed that the CPU data pins have a section in them that allows the chip to output data. These output lines seem to originate from a part of the chip that seems to select which input is to be output on the data pins. There seems to be 7 different inputs to t...

The wiki states that "This hard-wired second controller also contains a microphone, which gives an immediate 1-bit report at $4016 D2 whenever it is read." , but what does this status bit actually represent? Can the $4016 register be read literally any time or does it have to be strobed to update th...

While debugging code I noticed that the return address for a subroutine was pushed to $00:00FE - $00:00FF instead of $00:01FE - $00:01FF . As far as I have read, SNES should use page 1 for stack just like NES, but still it seems to go to zero page. Not sure if I need to post any code, but here is al...

So, about the problem I had earlier. Apparently I managed to fix the code itself, but because the debugger displayed it incorrectly I thought that it wasn't fixed.

So as a feature request:
Make the debugger detect whether 8 bit or 16 bit mode should be used and display the code accordingly.

I'm not sure if it was explained in the document, but the reason for the sprites "screwing up" happens when there are too many sprites on single scanline and the PPU ignoring some of them. The PPU considers sprites as 8x8 pixel regions regardless of the sprite size setting, so if you use 32x32 sprit...

Are you sure an interrupt vector isn't set to that address? I'll have to check that, but I'm pretty sure no, since they were defined with labels. All interrups should be disabled at that point anyway since it's part of the reset code. EDIT: Interrupts should be ruled out now. The address the progra...

1. The "sub start" lines indicate the start of a routine. That means that a JSR or JSL command jumped to that location. Then I'm not sure if it's bugged because in the code that I'm debugging it has: LDA #$FF STA $4305 --- sub start --- STA $4306 --- sub start --- LDA #$01 STA $420B Do you have mor...

I was debugging some code and I have a few questions about the debugger: 1. What are the "sub start" lines? 2. What is "call stack" used for? 3. Why does the debugger sometimes jump back in code when the opcode is not a jump/branch type opcode? This usually causes the code to get stuck in a short se...

I ran into a compilation error that I can't seem to figure out. The code does compile, but ca65 thinks is that the "RegisterSetup" subroutine should be compiled in index register 8 bit mode, instead of 16 bit mode, and compiles it incorrectly. I can't find what causes this error. Here is the code to...

Got the memory clear DMA working now. Since there are some registers that are split into two byte sized registers, can you use a 16 bit register mode to write to both at once? For the "write twice" type registers, is there a latch that resets which one is written? Iirc, this was done by reading $200...

If your stack pointer is in the cleared area, then that will also affect the value being read by PLB opcode. Not sure why I didn't think of this. Afaik using DMA would be faster than using MVN/MVP, and doesn't use the CPU registers for its operation. While I am a bit more familiar with DMAs than MV...