Search found 27 matches

by ace314159
Wed Jun 19, 2019 9:43 pm
Forum: NESemdev
Topic: A12 Timing Question
Replies: 4
Views: 6432

Re: A12 Timing Question

I had another question. I'm currently failing the scanline timing test, but if I delay the first sprite and BG tile fetches by 1 PPU cycle (reading sprite on 263 and BG on 327), it passes. I logged when I'm doing the reads and I'm doing them on the right cycle, and I passed the ppu_vbl_nmi tests. I'...
by ace314159
Wed Jun 19, 2019 5:57 pm
Forum: NESemdev
Topic: A12 Timing Question
Replies: 4
Views: 6432

Re: A12 Timing Question

Thank you! That makes much more sense.
by ace314159
Wed Jun 19, 2019 1:05 am
Forum: NESemdev
Topic: A12 Timing Question
Replies: 4
Views: 6432

A12 Timing Question

I am trying to understand when PPU A12 is changed in order to correctly implement the MMC3 IRQ, but I'm not understanding something. The wiki says that if using 8x8 sprites and BG uses $0000 and sprites use $1000, the IRQ counter should decrement on PPU cycle 260. However, when I look at the frame t...
by ace314159
Fri Jun 14, 2019 5:02 pm
Forum: NESemdev
Topic: Failing Blargg's MMC3 IRQ Tests
Replies: 6
Views: 6015

Re: Failing Blargg's MMC3 IRQ Tests

I figured it out! It turns out I wasn't supposed to reset the counter after writing to $E000. I guess I should've guessed that since the wiki says that the counter is unaffected, but the doc located at http://nesdev.com/mmc3.txt , had code showing that the counter was reset after writign to $E000. I...
by ace314159
Fri Jun 14, 2019 4:31 pm
Forum: NESemdev
Topic: Failing Blargg's MMC3 IRQ Tests
Replies: 6
Views: 6015

Re: Failing Blargg's MMC3 IRQ Tests

You're right! Those lines are wrong. I got confused and thought 0x1000 had a bit set in the 15th bit instead of the 12th bit, and so I shifted right by 15 to see if that bit was set. As a hack, I manually shifted the address from $2006 left 3 to make it work. I'm surprised the previous tests passed ...
by ace314159
Fri Jun 14, 2019 11:56 am
Forum: NESemdev
Topic: Failing Blargg's MMC3 IRQ Tests
Replies: 6
Views: 6015

Re: Failing Blargg's MMC3 IRQ Tests

I put an assert to ensure that IRQCounter is always nonzero before decrementing it, but it never caused an exception, so I'm pretty sure that that's not the cause. I tried to implement my code the same way you have yours, and it still stopped at the same error, but I noticed that your IRQ checking c...
by ace314159
Fri Jun 14, 2019 12:07 am
Forum: NESemdev
Topic: Failing Blargg's MMC3 IRQ Tests
Replies: 6
Views: 6015

Failing Blargg's MMC3 IRQ Tests

I'm trying to implement the MMC3 IRQ, but I'm failing the first of blargg's tests called clocking. I get the error "Should reload when clocked when counter is 0", but from my code I'm definitely reloading the counter. Looking at the source of the test, I'm presuming that it's a timing issue, but I'v...
by ace314159
Mon Feb 18, 2019 11:53 pm
Forum: NESemdev
Topic: $4017 Delay after Write Contradiction?
Replies: 3
Views: 5061

Re: $4017 Delay after Write Contradiction?

Are APU "read" phases during the even CPU cycle? If so, does that mean there's either a 0 or 1 cycle delay between writing to $4017 and resetting the frame counter?
by ace314159
Mon Feb 18, 2019 10:01 pm
Forum: NESemdev
Topic: $4017 Delay after Write Contradiction?
Replies: 3
Views: 5061

$4017 Delay after Write Contradiction?

On this page , it says that the effects of writing to $4017 (resetting the frame counter) occur after 3 or 4 CPU cycles, but on here , it says that it occurs after 2 or 3 cycles. And then, on the same page in the following sentence, it says that the effect is immediate. Which one is correct or am I ...
by ace314159
Sun Feb 17, 2019 5:18 pm
Forum: NESemdev
Topic: Cracking Sound for APU
Replies: 12
Views: 7254

Re: Cracking Sound for APU

I decided to just output an audio sample every number of cycles and increase the sample rate to 48000 from 44100, and it seemed to get rid of most of the crackling. To get rid of the last bit, I decided to add CPU timing to limit the framerate to 60.09, and that seems to get rid of the other crackli...
by ace314159
Sat Feb 16, 2019 10:59 pm
Forum: NESemdev
Topic: Emulating CPU activity per cycle
Replies: 4
Views: 8592

Re: Emulating CPU activity per cycle

There's also a 6502 manual that goes over what occurs during each clock cycle of the addressing mode. That information is under Appendix E, but I think reading the other parts wouldn't be a waste since it explains the CPU pretty well. This document also goes over what occurs during each clock cycle ...
by ace314159
Sat Feb 16, 2019 1:20 am
Forum: NESemdev
Topic: Cracking Sound for APU
Replies: 12
Views: 7254

Re: Cracking Sound for APU

If I'm forced to choose one, I'd rather choose the one timed with a timer instead of counting the clock cycles. However, the audio is practically unrecognizable if I do it that way because there is almost as much crackling as there is useful sound. Am I using the wrong function or algorithm to time ...
by ace314159
Sat Feb 16, 2019 12:39 am
Forum: NESemdev
Topic: Cracking Sound for APU
Replies: 12
Views: 7254

Cracking Sound for APU

I've mostly implemented the APU, but I'm unsure of how to implement the timing of actually outputting crisp sound. First, I tried to calculate the number of APU cycles per sample (NTSC_FREQ / sampleRate), and that worked pretty well, but there was minor crackling when VSync was on. When there was no...
by ace314159
Thu Jul 26, 2018 11:47 am
Forum: NESemdev
Topic: Handling Writing to ROM or out of range addresses
Replies: 15
Views: 11964

Re: Handling Writing to ROM or out of range addresses

I'll make sure to remember that.

Looking at it again, I noticed that for OAM and CHR RAM it mentions a "pattern". What does this mean?
by ace314159
Thu Jul 26, 2018 11:11 am
Forum: NESemdev
Topic: Handling Writing to ROM or out of range addresses
Replies: 15
Views: 11964

Re: Handling Writing to ROM or out of range addresses

That's definitely out of the scope of my emulator, but I understand what a power cycle and reset does now. Thanks for the help!