Search found 224 matches

by creaothceann
Sun Feb 10, 2019 3:44 pm
Forum: SNESdev
Topic: Vram usage for mixed modes
Replies: 3
Views: 4429

Re: Vram usage for mixed modes

Or just use vSNES.
by creaothceann
Tue Jan 01, 2019 5:13 pm
Forum: SNESdev
Topic: H-blank emulator inaccuracy
Replies: 12
Views: 11467

Re: H-blank emulator inaccuracy

paulb_nl wrote:All consoles: Showing left half Incorrect behaviour& right half correct behavior screen.
https://i.imgur.com/bpuXsI4.png
Same on my SFC.
by creaothceann
Sat Dec 22, 2018 3:47 pm
Forum: SNESdev
Topic: GSS hanging on hw, spc quirk?
Replies: 23
Views: 13262

Re: GSS hanging on hw, spc quirk?

There is no exe, as in you need to compile it if you want one. Can I expect that developers of retro console games who use Windows will either have already installed MinGW-w64 and MSYS2 or be willing to install them? Of course not. That'd be a barrier. /s I wonder if people would install Free Pasca...
by creaothceann
Sun Dec 16, 2018 6:06 pm
Forum: SNESdev
Topic: SNES clock change
Replies: 8
Views: 10234

Re: SNES clock change

*bump* Seems that the 65c816's PHI1 really takes 3 full master clock cycles. I've also found some info about why the 65c816 might not have been clocked faster than ~3.58MHz: "REP and SEP had timing problems, possibly due to layout (rather than, say, logical design, or a pipelining mistake)" . They "...
by creaothceann
Sun Dec 02, 2018 2:31 am
Forum: SNESdev
Topic: How can the SNES background be distorted without mode 7?
Replies: 5
Views: 5262

Re: How can the SNES background be distorted without mode 7?

Like a lot of effects on the SNES, this sort of thing can be done by changing parameters (such as scrolling, colors, etc.) while the screen is being drawn. For instance, for the sinusoidal effect, between each scanline (row of pixels) of the screen being displayed on the TV, the background layer is...
by creaothceann
Mon Nov 19, 2018 1:56 am
Forum: SNESdev
Topic: Wich could have been an realistically accurate SNES by DATE?
Replies: 45
Views: 24905

Re: Wich could have been an realistically accurate SNES by D

Read and write in the SNES are fully simultaneous. I thought I'd read that they weren't. MVN/MVP (already implemented by the 65c816 core itself, not the 5A22) reads a byte in one cycle and writes it in the next. As fas as the 65c816 is concerned, there is only one address bus. In that case, it shou...
by creaothceann
Sun Nov 18, 2018 2:13 am
Forum: SNESdev
Topic: Wich could have been an realistically accurate SNES by DATE?
Replies: 45
Views: 24905

Re: Wich could have been an realistically accurate SNES by D

Right, afaik you need 2 phases because it's a bidirectional bus. You could read/write in every phase if you had an outgoing "write" data bus and an incoming "read" data bus - of which only one would be active at a time except (maybe) for Read-Modify-Write instructions.
by creaothceann
Sat Nov 17, 2018 1:13 pm
Forum: SNESdev
Topic: Wich could have been an realistically accurate SNES by DATE?
Replies: 45
Views: 24905

Re: Wich could have been an realistically accurate SNES by D

Also, part of the reason is the 8-bit data bus. If the 65c816 would use 16 bits per memory access like the 68k, it'd be much faster...
by creaothceann
Thu Nov 08, 2018 10:48 am
Forum: SNESdev
Topic: blargg's SPC test ROMs
Replies: 34
Views: 26613

Re: blargg's SPC test ROMs

Super Famicom (switched to PAL):
spc_dsp6 either fails with the same error as above, or it hangs at (after?) the "Misc/counter rate synchronizations" step; the other tests pass.

Super Nintendo (PAL):
Same as above, except that the error is "Failed 02".
by creaothceann
Thu Nov 08, 2018 5:07 am
Forum: SNESdev
Topic: blargg's SPC test ROMs
Replies: 34
Views: 26613

Re: blargg's SPC test ROMs

Kingizor wrote:In that post you mention having two consoles so I might assume you tested the 1992 console?
No, the 1993 one (Super Famicom, switch set to "NTSC"). The PAL console is not connected often.

I'll do some more tests later.
by creaothceann
Wed Nov 07, 2018 11:27 am
Forum: SNESdev
Topic: blargg's SPC test ROMs
Replies: 34
Views: 26613

Re: blargg's SPC test ROMs

Only the spc_dsp6 test fails for me:

Image
by creaothceann
Wed Nov 07, 2018 10:43 am
Forum: SNESdev
Topic: Trying to use TILE LAYER PRO
Replies: 25
Views: 12514

Re: Trying to use TILE LAYER PRO

open the game in ZSNES and play to the point where the palette you want is shown on screen (usually meaning going to the same place in-game where the tiles you want to view are actually used), and take a save state. Then in YY-CHR you can import the .zst file. As far as the data you posted, I guess...
by creaothceann
Thu Oct 04, 2018 2:41 am
Forum: SNESdev
Topic: Legality of the snes font?
Replies: 14
Views: 7490

Re: Legality of the snes font?

You could ask neologix about it: https://board.byuu.org/viewtopic.php?f=6&t=921
by creaothceann
Sun Sep 30, 2018 5:18 am
Forum: SNESdev
Topic: Converting a Lorom pcb cart to a hirom pcb cart
Replies: 27
Views: 16759

Re: Converting a Lorom pcb cart to a hirom pcb cart

I'm reading that inside of the header (64 Bytes), there is a Byte called "ROM layout" that determines what kind of memory ROM uses the game (LoROM, HiROM, ExLoROM, ExHiROM, fastROM, or slowROM). The SNES doesn't care about the header except for the interrupt pointers. The rest could be completely b...
by creaothceann
Thu Sep 27, 2018 12:11 am
Forum: SNESdev
Topic: Wich could have been an realistically accurate SNES by DATE?
Replies: 45
Views: 24905

Re: Wich could have been an realistically accurate SNES by D

Ok so if the SNES doesn't use the Phi1 cycle for anything or access internally.. then why don't the expansion chips use that half of the bus instead of blocking the CPU when they want to access the RAM/ROM sigh... Afaik the Phi1 phase (it's one half of a clock cycle) is used to set up the address b...