Search found 238 matches

by Fiskbit
Tue Dec 08, 2020 6:39 pm
Forum: NESdev
Topic: Vs System Shared Memory
Replies: 48
Views: 6393

Re: Vs System Shared Memory

Maybe something like this? "On the primary CPU, controls which CPU can access 2 KiB of shared RAM mapped in the $6000-7FFF region. When high, only the primary CPU can access the shared RAM. When low, only the secondary CPU can. The CPU that cannot access the shared RAM sees open bus." It was not ent...
by Fiskbit
Sun Dec 06, 2020 8:27 pm
Forum: NES Hardware and Flash Equipment
Topic: Famicom Network System (aka Famicom Modem) Investigations
Replies: 85
Views: 43941

Re: Famicom Network System (aka Famicom Modem) Investigations

The test looks good to me. Another thing I'm interested in seeing is whether $40C0.7 starts as 0 and becomes 1, which this test may not show because of the long wait for PPU init before the register read loop. If $40C0.7 is a CIC input, the lock CIC may wait for the key CIC to do something before ou...
by Fiskbit
Sat Dec 05, 2020 2:35 am
Forum: Newbie Help Center
Topic: The problem when writing 0 to $C000 in the real MMC3
Replies: 12
Views: 2529

Re: The problem when writing 0 to $C000 in the real MMC3

Ah, thank you! That makes sense. I think this does match blargg's explanation, then, and you didn't encounter it on values larger than 0 because there were at least 2 clocks between each $C001 write, preventing the issue.
by Fiskbit
Sat Dec 05, 2020 1:23 am
Forum: Newbie Help Center
Topic: The problem when writing 0 to $C000 in the real MMC3
Replies: 12
Views: 2529

Re: The problem when writing 0 to $C000 in the real MMC3

That's what I get for skipping over the quote assuming it was just a previous post. :) That's very interesting behavior. The OR with #$80 seems to match what's shown in the picture, but it looks like it was able to do 4 scanlines each time before encountering the problem, and it sounds like it only ...
by Fiskbit
Fri Dec 04, 2020 11:12 pm
Forum: Newbie Help Center
Topic: The problem when writing 0 to $C000 in the real MMC3
Replies: 12
Views: 2529

Re: The problem when writing 0 to $C000 in the real MMC3

Do we understand what the quirk actually is? I've been going over the IRQ, counter, and reload behavior in the wiki and looking at the timing of the ROM and it's not clear to me what's happening. The results (two bars of what looks like 4 scanlines) are also really weird. (Also, in rereading the wik...
by Fiskbit
Fri Dec 04, 2020 7:07 am
Forum: Reproduction
Topic: Using the INL device to dump SNES carts then flash ROM hacks of them
Replies: 5
Views: 4128

Re: Using the INL device to dump SNES carts then flash ROM hacks of them

I only just got an INL dumper recently, but I think you should be able to dump those with no problem, using a command such as: inlretro.exe -s scripts/inlretro2.lua -c SNES -d "path/to/file". You may need to specify hirom or lorom (e.g. -m hirom), but it might be able to do it automatically. For som...
by Fiskbit
Sat Nov 28, 2020 11:16 pm
Forum: NESdev
Topic: Vs Dualsystem Watchdog Timer
Replies: 21
Views: 4022

Re: Vs Dualsystem Watchdog Timer

I've been looking into this a bit to help figure out why the watchdog is triggering here and am finding myself rather confused about how Vs. games work in general. The wiki says the secondary CPU is in charge of providing the heartbeat, but also seems to imply that only DualSystem games have two CPU...
by Fiskbit
Sat Nov 28, 2020 9:47 pm
Forum: NESdev
Topic: Vs Dualsystem Watchdog Timer
Replies: 21
Views: 4022

Re: Vs Dualsystem Watchdog Timer

I interpret the wiki as saying that the watchdog is causing reset to be asserted on the CPUs and the PPUs, and also resetting a separate register at $4020 for coin counting. If the watchdog triggers, your game will be reset as though the reset button were pressed on a frontloader, taking you back to...
by Fiskbit
Thu Oct 29, 2020 6:39 pm
Forum: NESdev
Topic: Interrupt disrupting my MMC1 bankswap
Replies: 3
Views: 3346

Re: Interrupt disrupting my MMC1 bankswap

The code you've posted makes it a bit hard to be sure what's going on, since it's lacking addresses (so branch targets are unspecified) and the interrupt handler isn't present. That said, you'll need to be resetting the shift register both unconditionally in the interrupt before writing to MMC1 (bec...
by Fiskbit
Tue Oct 13, 2020 3:10 pm
Forum: NESdev
Topic: 6502 vdelay - cycle delay routine with variable length at runtime
Replies: 37
Views: 13468

Re: 6502 vdelay - cycle delay routine with variable length at runtime

Luck is a big part of this level of optimization. :) These seem very lean now. Really cool that the 16-bit one only needs 2 extra cycles. Looking at vdelay_modify.s, I think if you move vdelay_toolow to the end, you can use #$18 (CLC) as the clockslide's branch operand/instruction and put the vdelay...
by Fiskbit
Mon Oct 12, 2020 1:43 am
Forum: NESdev
Topic: 6502 vdelay - cycle delay routine with variable length at runtime
Replies: 37
Views: 13468

Re: 6502 vdelay - cycle delay routine with variable length at runtime

I came up with another improvement. Since the problem with clockslide is that odd lengths will read from $EA, which could have side effects, I've opted to change the instruction to an always-taken branch, which is also 2 bytes and takes 3 cycles. The operand needs to both lead to an RTS instruction ...
by Fiskbit
Sun Oct 11, 2020 11:25 pm
Forum: NESdev
Topic: 6502 vdelay - cycle delay routine with variable length at runtime
Replies: 37
Views: 13468

Re: 6502 vdelay - cycle delay routine with variable length at runtime

Sure, please use these if they're useful! When I can, I like to license my code as permissively as possible. Attribution is not necessary, but if you'd like, you're welcome to credit me as Fiskbit. I do have a github profile , but don't have anything public on it at this time. I can look at extendin...
by Fiskbit
Sun Oct 11, 2020 10:43 pm
Forum: NESdev
Topic: 6502 vdelay - cycle delay routine with variable length at runtime
Replies: 37
Views: 13468

Re: 6502 vdelay - cycle delay routine with variable length at runtime

I made a self-modifying version that requires a 33 cycle minimum. I don't have ideas at the moment for further improvements. VDelay_RAM := $6000 VDELAY_MINIMUM = 33 ; Waits for A cycles. JSR/RTS is included. Minimum is 33 cycles. ; Input: A: Number of cycles to delay. ; Clobbers: A/Y VDelay: ; +6 = ...
by Fiskbit
Sun Oct 11, 2020 8:14 pm
Forum: NESdev
Topic: 6502 vdelay - cycle delay routine with variable length at runtime
Replies: 37
Views: 13468

Re: 6502 vdelay - cycle delay routine with variable length at runtime

I tweaked my clockslide code to operate like yours and to use RTS and the stack and got 46 cycles in total. If you can guarantee that VDelay_Clockslide starts at $xx01, then you can shave off another 2 cycles by removing the ADC. VDELAY_MINIMUM = 46 ; Waits for A cycles. JSR/RTS is included. Minimum...
by Fiskbit
Sat Oct 10, 2020 10:01 am
Forum: NESdev
Topic: 6502 vdelay - cycle delay routine with variable length at runtime
Replies: 37
Views: 13468

Re: 6502 vdelay - cycle delay routine with variable length at runtime

I haven't fully digested the code yet, but it looks pretty neat. Have you considered using a clockslide instead of the jump table for delaying 0-7 cycles? You could put an 8-byte clockslide between vdelay_low and vdelay_low_rest and remove 3 cycles of overhead by not needing to jump to vdelay_low_re...