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 Post subject: about Brad Taylor's ref
PostPosted: Thu Jan 26, 2006 7:49 am 
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Location: Shanghai,China
In Brad Taylor's ref, he said:"the PPU fetches an attribute table byte for every 8 sequential horizontal pixels it draws."

why 8? i think it should be 32 because one attribute table byte contain all the high 2 bit for a 4*4 tiles group. help me please.


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PostPosted: Thu Jan 26, 2006 10:19 am 
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It is true that one set of attribute bits applies to 4 tiles at once, but the PPU has no such buffers inside it - as such, it will re-fetch the same attribute bytes for all of the appropriate tiles.

The upside to this is that it makes the MMC5's "extended attribute" mode possible (which uses extra RAM to allow setting per-tile attribute data).

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PostPosted: Thu Jan 26, 2006 9:56 pm 
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Thanks Quietust, I understand it. You have explained it very clearly :)


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PostPosted: Thu Jan 26, 2006 10:08 pm 
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In fact, if you wanted to make your own video-processor-in-an-FPGA, you could in theory make it support attribute cells that are 8x1 pixels in size, like those on the MSX.


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