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PostPosted: Sun Apr 23, 2006 10:29 am 
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Joined: Mon Mar 06, 2006 3:42 pm
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Location: Montreal, canada
Hi,

In regards to the question that started this thread... Does anyone know where I can find:

(1) an exact list of the instructions supported by the NMOS 6502-based CPU in the Nintendo Entertainment System, including any undocumented instructions? (This document doesn't look too bad, except that it includes 6510/8502/other instructions and I don't want to get confused.)

(2) exact timings for those NMOS 6502 instructions? (In particular the datasheets for CMOS 6502s such as W65C02S are no good for this)

I need this information to write up an abstract specification of the timing templates of the NES CPU instructions for myself, to feed to a crazy code generator thing. I would prefer not to rely on what others have implemented in their NES emulators, but if that is the easiest way to get a reliable list then I might resort to that.


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PostPosted: Sun Apr 23, 2006 11:18 am 
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1) This page is probably the easiest/best quick look-up reference for supported instructions, their addressing modes, and opcodes. As for "undocumented" opcodes, my primary reference was this doc since it seemed the most logical and consistent. However it's not exactly layed out in an eye-friendly manner, so I used this doc to match instructions/modes to their respective opcodes (but relied on the first doc for the behavior of the instructions).

Be warned since there aren't official names for these instructions, the naming in each doc differs slightly, so you'll have to be careful not to mix up instructions.

2) That's what the doc you linked to is so good at. Since the number of cycles an instruction requires (along with the task it performs) depends on the addressing mode and not the instruction (usually, some implied mode instructions are exceptions), you can use this doc to see what the CPU is doing for each cycle within the instruction.

For example Absolute Reads are always 4 cycles (1 to fetch op, 1 to read low byte, 1 to read high byte, 1 to read from target address)... regardless of the instruction (ADC, ORA, LDA, LDX, etc -- all behave the same way as far as timing and fetches go)

Just note that there are 3 applications to most addressing modes and they're all timed differently. Absolute,X mode for example will operate differently for each Read (LDA, ORA, etc), Write (STA), and Read/Modify/Write (INC, ASL, etc). But that's all covered in 6502_cpu.txt


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PostPosted: Sun Apr 23, 2006 12:54 pm 
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Joined: Mon Mar 06, 2006 3:42 pm
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Location: Montreal, canada
Thanks Disch. I'll see what I can do with those.

Edit: the first link was useful, I got exactly 151 insns from it so that is reassuring.

I'll try and figure out the other 105 opcodes later (taking a short detour to try and get my SPC700 info into a similar format).


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