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sprdma_and_dmc_dma test help needed
http://forums.nesdev.com/viewtopic.php?f=10&t=14411
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Author:  Alyosha_TAS [ Wed Jun 15, 2016 12:09 pm ]
Post subject:  sprdma_and_dmc_dma test help needed

Hello NesDev :)

I am working on an emulator and this test has me stumped. If anyone can offer any advice I would really appreciate it.

So far the emulator passes the DMC basics test, so I'm pretty sure I'm on the right track in working out the DMC and DMA timings, but this test hangs on me every time.

It is getting hung up here:
Code:
E232  A9 LDA #$1F        A:00 X:00 Y:00 P:37 SP:F0 Cy:1263851 TBIZC
E234  8D STA $4015       A:1F X:00 Y:00 P:35 SP:F0 Cy:1263853 TBIC
E237  A9 LDA #$10        A:1F X:00 Y:00 P:35 SP:F0 Cy:1263857 TBIC
E239  2C BIT $4015       A:10 X:00 Y:00 P:35 SP:F0 Cy:1263859 TBIC
E23C  D0 BNE $E22B       A:10 X:00 Y:00 P:35 SP:F0 Cy:1263863 TBIC


The state of the DMC at STA $4015 is:

Sample Buffer filled: TRUE
Bits remaining in Sample: 0
Current Remaining: 0
Timer Value: 6

So what keeps happening is that at STA$4015, the DMA that is supposed to occur to pass the BIT test is delayed because the buffer is still full. This loop just repeats and ends up in this exact state infinitely. This is at frame 45, so SPRDMA's haven't even started yet, it seems I can't get past the setup steps.

I THINK I might be going wrong where the initial setup around frame 43:

Code:
E206  A9 LDA #$0F        A:00 X:00 Y:00 P:37 SP:EE Cy:1260221 TBIZC
E208  8D STA $4010       A:0F X:00 Y:00 P:35 SP:EE Cy:1260223 TBIC
E20B  8D STA $4015       A:0F X:00 Y:00 P:35 SP:EE Cy:1260227 TBIC
E20E  A9 LDA #$1F        A:0F X:00 Y:00 P:35 SP:EE Cy:1260231 TBIC
E210  8D STA $4015       A:1F X:00 Y:00 P:35 SP:EE Cy:1260233 TBIC
E213  EA NOP             A:1F X:00 Y:00 P:35 SP:EE Cy:1260237 TBIC
E214  8D STA $4015       A:1F X:00 Y:00 P:35 SP:EE Cy:1260242 TBIC
E217  A9 LDA #$10        A:1F X:00 Y:00 P:35 SP:EE Cy:1260246 TBIC
E219  2C BIT $4015       A:10 X:00 Y:00 P:35 SP:EE Cy:1260248 TBIC


My guess is that I'm doing something wrong with the DMC state around the 2 consecutive $4015 writes, but I don't know what.

So I guess my first questions are, what should the state of the DMC be after the second STA $4015? What should the state be when BIT test happens at E239?

Thanks in advance for any insights!

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