Will continue to work this weirdness out.
edit: Fiskbit, (Thank you Fiskbit! ), sheds light on this problem in Sour’s Mesen thread:
So, it seems that implementing thefox’es code ideas, link on the bottom of that linked nesdev wiki page, is crucial to solve this problem. ...However, rendering and vblank interrupt are disabled, so vblank’s nmi isn’t destroying MMC1’s 5-write serial register, right? I’ll find out later today.Fiskbit wrote: ↑Tue Sep 22, 2020 4:21 pmDifferent serial registers have different ways of handling the serial writes. w is used specifically for the $2005 and $2006 PPU writes, which take 2 writes. You're correct that interrupts can be a big problem for serial registers; if the handler needs to use a serial register that is also used outside the interrupt, then the two might interfere with each other. This also happens in cases like MMC3, where you write to two different registers to do something like swap banks.
MMC1 has a 5-write serial register, but this isn't using the w bit in the PPU; it has its own method of tracking the 5 writes. Unfortunately, Mesen doesn't allow you to see the interior state of a mapper. There's a ton of mappers and they all have their own registers and behavior, so it's not an easy thing to expose. As a result, it's a bit hard to debug MMC1 issues where your number of writes is wrong.