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PostPosted: Wed Jan 25, 2006 2:46 am 
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hi,all.I have read Brad Taylor's 2C02 reference very carefully.but i still have some confusion which i list below:

1.i can't understand the top row of the diagram. why there is some space between two digit?

2.what is the temp vram register in Loopy's article?and what's the difference between vram register and temp vram register?


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PostPosted: Wed Jan 25, 2006 8:05 am 
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*Groans*

Some new members of this forum don't seem to realise that there is a noob board. Please post there dude.

http://nesdev.com/loopyppu.zip

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 Post subject: thank you man
PostPosted: Wed Jan 25, 2006 8:26 am 
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thank you WedNESday :) i will post to the newbie help center next time.but could you please answer the questions i asked in this post?i really need the answer,thank u man.


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PostPosted: Wed Jan 25, 2006 9:19 am 
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No problem. Try here http://nesdev.com/bbs/viewtopic.php?t=418 for information on the diagram (i've never used it myself).

Have you downloaded and read the link that I provided? Well, when data is written to $2005/$2006 the data does not appear there instantly. It goes into a temporary VRAM register and only gets transferred into the original VRAM register at certain times. Both registers are 15-bits wide (yes, the VRAM register with 0x3FFF memory is 15-bits wide, which allows you to access 0x7FFF of memory but it wraps anyway, this is to allow for FineY scroll).

On PPU cycle 257 (if the background or sprites are enabled) or the second write to $2006, the VRAM register equals the temporary VRAM register.

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PostPosted: Wed Jan 25, 2006 11:14 am 
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WedNESday wrote:
On PPU cycle 257 (if the background or sprites are enabled) or the second write to $2006, the VRAM register equals the temporary VRAM register.


Note that on cycle 257 only the X-scroll related bits are copied to the real VRAM register (bits 0-4, 10). Other bits are unaffected.

The only time the address is copied in full (aside from the second $2006 write) is on the pre-render scanline on cycle 304.


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PostPosted: Wed Jan 25, 2006 12:38 pm 
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D'oh. My bad.

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PostPosted: Wed Jan 25, 2006 9:20 pm 
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thank you.I think i have grasp the idea with your help.what i want to add is in Brad Taylor's ref,he never mention the "LoopyV" and "LoopyT" register.instead,he did mention 5 counters(HT, VT, H, V, FV) which i thought have been "connected" to $2006.and PPU use these 5 counters to address name table,attribute table,etc.i guess these 5 counters is LoopyV.these 5 counters also have their own latch which i thought is LoopyT.I have compared Loopy's ariticle and Brad Taylor's many times and then at last form this idea. is this idea correct?sorry for my poor english:)


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PostPosted: Wed Jan 25, 2006 9:51 pm 
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JJ.Loki wrote:
sorry for my poor english:)


I'm sorry, I really wish I could help you with your actual problem, but I don't know too much about what you guys are talking about here. But I just wanted to say, I wouldn't have known that you were from a different country right off the bat if you didn't:

a. Have your location specified on your profile
b. Not put a space after every period.

You speak pretty okay english. Nothing's as bad as my japanese. Ask Quietust, haha.


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PostPosted: Thu Jan 26, 2006 4:25 am 
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Celius are you writing a NES emulator? If so then you must get to grips with things like that.

The 15-bit VRAM Address is made up of the five counters, which is why it is 15-bits wide evn though the memory is only 14-bits wide.

Here is the layout of the counters; (correct me if I am wrong)

bits 0-4;

are the horizontal tile number that is incremented 32 times a scanline

bits 5-9;

are the vertical tile number that is incremented 30 times a frame

bits 10-11

are the name table select bits

0-0 Name Table 0
0-1 Name Table 1
1-0 Name Table 2
1-1 Name Table 3

bits 12-14

are the Fine Y scroll. This is basically chooses which vertical line of the tile to draw.

FineX (a 3-bit PPU register)

The FineX scroll of the tile being drawn.

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 Post subject: i think so too
PostPosted: Thu Jan 26, 2006 6:07 am 
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yes,i agree.what u said is as same as what Brad Taylor said in his reference. another question,fineX scroll is not the member of loopyV,but PPU itself use fineX scroll internally to render frames.is this right?


Last edited by JJ.Loki on Thu Jan 26, 2006 6:19 am, edited 2 times in total.

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PostPosted: Thu Jan 26, 2006 6:14 am 
i read lots of documentation and i read about bank switching... i read any demos in asm.. mys question is: what happen .. because any demos are 16 kb prg (1 bank?) and 8kb chr (1 bank?).... if nes header is 1 16kb prg means 1 bank of 16 kb prg???.. i am confused because demos with 1 16 kb prg have code for nesasm saying: .bank 0 xxx... .bank 1 xxx .bank2 xxxxx (for writing characters fonts).. what happen?? if rom is only 1 bank 16 prg!!!.. what more banks than only 1??


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PostPosted: Thu Jan 26, 2006 10:12 pm 
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NESASM banks are always 8 KB no matter the capabilities of the mapper you're targeting. What you're seeing with an NROM that takes 3 NESASM banks is one bank loaded into CPU $8000 and $C000, one bank loaded into CPU $A000 and $E000, and one bank loaded into PPU$0000.


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PostPosted: Fri Jan 27, 2006 11:14 am 
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lord_nes wrote:
i read lots of documentation and i read about bank switching... i read any demos in asm.. mys question is: what happen .. because any demos are 16 kb prg (1 bank?) and 8kb chr (1 bank?).... if nes header is 1 16kb prg means 1 bank of 16 kb prg???.. i am confused because demos with 1 16 kb prg have code for nesasm saying: .bank 0 xxx... .bank 1 xxx .bank2 xxxxx (for writing characters fonts).. what happen?? if rom is only 1 bank 16 prg!!!.. what more banks than only 1??


Whoa, let's stay on topic please. First of all did you understand my previous post? If not I'll redo another one. As for the FineX scroll it is a PPU register that is 3-bits wide and is not part of the VRAM address. Do you understand what the shift registers are within the PPU? If you don't then you won't understand how FineX works.

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