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PostPosted: Thu Jul 12, 2018 7:11 am 
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I've been reading the second of two snes manuals and in this book it first states that the SRAM on a Super Accelerator System is 2Mbyte, but later states that the maximum is only 2Mbit.
I assume that either I'm misreading something somewhere, or that the 2Mbyte is a typo, as the fullsnes doc only has a certain amount of sram address lines.
Can anyone clear this up for me?

Thanks,
~Molive


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PostPosted: Thu Jul 12, 2018 11:04 am 
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2Mbyte is either a typo, or it might refer to the maximum supported size. The actual manufactured carts don't have 2Mbyte.
I think the PCB with biggest sram capacity is SHVC-1L8B-10, the "8" would indicate 256Kx8 (=2Mbit), but as far as I know the PCB is actually fitted with a 64Kx8 chip. And all other SA1 PCB's have even smaller SRAMs, with 8Kx8 and 32Kx8.
In fullsnes, I have guessed A16 and A18 to exist, for 2Mbyte one would additionally need A17, A19, A20, but there are only two spare pins, so 2Mbyte looks pretty much impossible (unless it's sharing pins for multiple purposes, but the rest of the design doesn't look as if it's supposed to share pins).
On the other hand, if it's max 256Kbyte, then the guessed A18 pin is more likely A17 (plus some of the guessed pins might be swapped).


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PostPosted: Thu Jul 12, 2018 11:50 am 
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I assume this is talking about BW-RAM ("backup RAM"), and that by "SRAM" the OP means "SA-1 RAM that is battery-backed" (rather than the actual memory type of Static RAM, which BW-RAM is!).

It's megabits. The megabytes unit -- shown in the first below picture -- was likely a mistake on the part of the person doing the documentation, or someone erroneously wrote "MB" instead of "Mb" somewhere pre-doc-writing.

Some, but not all, evidence is below -- you can clearly see that memory map/address map-wise, there's no way this would work. The nail-in-the-coffin is the $2228 write protection register, IMO.

There are other typos or oddities too, I believe. Like the memory map diagrams in Sections 3.1 (SNES CPU) and 3.2 (SA-1 CPU). The former says "BW-RAM AREA 2M Bits Max" for $400000 to $43FFFF, while the latter says "BW-RAM AREA 4M Bits Max" for the same address range. 4 banks of 64KBytes = 256KBytes = 2Mbits. However, see my final 2 paragraphs in this post. Another is Section 3.3.3, which for some reason omits the 2Mbit line (40:0000h~43:FFFFh).

Possibly these errors/oddities were fixed in a later revision of the manual, but obviously that one is not commonly available, so you're stuck with what you got.

One thing that's confusing to me -- and maybe this is another typo/mistake, unsure because I lack SA-1 familiarity -- is to review Section 4.1.20 (register $2224) and 4.1.21 (register $2225) carefully: $2224 is BW-RAM mapping for the SNES CPU side, which looks like it ranges from banks $40 to $43. $2225 is for the SA-1 side, and something else entirely. Banks $40 to $43 are what you'd expect, but then $60 to $6F are a different "block size", based on bit 7 of $2225.

If someone understands this, and I imagine several folks do, don't put too much time into explaining it (honest!) since SA-1 doesn't interest me and I don't want folks wasting cycles explaining it to me. But part of me wonders if that could somehow explain the dilemma; maybe it's a case of "total capability" vs. "what we actually implemented". If so, wouldn't surprise me, lots of vendors do this sort of stuff; marketing saying "our device can address up to 256 MBytes!" even though register-wise and address-line-wise it only supports 1/4th of that. :-)


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PostPosted: Thu Jul 12, 2018 4:37 pm 
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It's a max of 2mbits capable, as in, there are enough address lines (A0-A17) but there were only 2 Japanese games that used a 1mbit sram (A0-A16). The 1L8B I have seen with 1mbit and 512k srams mounted on them. Beyond these two 1mbit sram games, there's a few that use 512k, otherwise all the others are 256 and 64k (1L5b and 1L3b respectively).


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PostPosted: Thu Jul 12, 2018 6:39 pm 
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Anything above 1mbit BW-RAM 32mbit ROM requires the Super MMC decoder which is found on the chip. As far as I'm aware no game used anything requiring this amount, so I'm not sure if emu devs have fully implemented it. :p

Thanks for clearing this up guys. It seems there's a few places where the manual isn't perfect.

~Molive


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PostPosted: Fri Jul 13, 2018 10:40 am 
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To summary, official docs specify five different capacities: 1Mbit, 2Mbit, 4Mbit, 8Mbit, and 16Mbit (plus some sentences without clear meaning). Going by that, SA-1 CPU is allowed to access more memory than SNES CPU, and capacity might vary for access via xx:6000h or 40:0000h. Or, the specs contain mistakes, or they forgot to update some sections for reflecting the final chip design/pinout.
Code:
book2 on max BW-RAM capacity
  section  quotes                         ;meaning
  1.1      "2 Mbytes of RAM"              ;16Mbit
  3.1      "2M Bits Max"                  ;2Mbit (for SNES side)
  3.1      "(00)-(1F)" (in 8Kbyte units)  ;2Mbit (for SNES side)
  3.2      "4M Bits Max"                  ;4Mbit (for SA-1 side)
  3.2      "(00)-(7F)" (in 8Kbyte units)  ;8Mbit (for SA-1 side)
  3.3.3    "1M RAM: 40:0000H-41:FFFFh"    ;1Mbit
  3.3.6    "do not apply ... 2 Mbits"     ;(not)2Mbit (for "MMC emulation")
  4.1.20   "00-1F" (in 8Kbyte units)      ;2Mbit (for SNES side)
  4.1.21   "32 blocks" (in ??Kbyte units) ;(?)Mbit (for SA-1 side)
  4.1.21   "128 blocks" (in 8Kbyte units) ;8Mbit (for SA-1 side)
  4.1.24   "400000-43FFFF 2M" "(bits)"    ;2Mbit (write-protectable)
  4.1.24   Initial "FFH" = "all areas"    ;(all)MBit (write-protectable)

Basically, 2Mbit and 2Mbyte might be both wrong, and the actual capacity might be anything else. One could do scope tests & software tests to find out what memory accesses are possible... but well, there isn't too much practical use for gaining that info.


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