To summary, official docs specify five different capacities: 1Mbit, 2Mbit, 4Mbit, 8Mbit, and 16Mbit (plus some sentences without clear meaning). Going by that, SA-1 CPU is allowed to access more memory than SNES CPU, and capacity might vary for access via xx:6000h or 40:0000h. Or, the specs contain mistakes, or they forgot to update some sections for reflecting the final chip design/pinout.
Code:
book2 on max BW-RAM capacity
section quotes ;meaning
1.1 "2 Mbytes of RAM" ;16Mbit
3.1 "2M Bits Max" ;2Mbit (for SNES side)
3.1 "(00)-(1F)" (in 8Kbyte units) ;2Mbit (for SNES side)
3.2 "4M Bits Max" ;4Mbit (for SA-1 side)
3.2 "(00)-(7F)" (in 8Kbyte units) ;8Mbit (for SA-1 side)
3.3.3 "1M RAM: 40:0000H-41:FFFFh" ;1Mbit
3.3.6 "do not apply ... 2 Mbits" ;(not)2Mbit (for "MMC emulation")
4.1.20 "00-1F" (in 8Kbyte units) ;2Mbit (for SNES side)
4.1.21 "32 blocks" (in ??Kbyte units) ;(?)Mbit (for SA-1 side)
4.1.21 "128 blocks" (in 8Kbyte units) ;8Mbit (for SA-1 side)
4.1.24 "400000-43FFFF 2M" "(bits)" ;2Mbit (write-protectable)
4.1.24 Initial "FFH" = "all areas" ;(all)MBit (write-protectable)
Basically, 2Mbit and 2Mbyte might be both wrong, and the actual capacity might be anything else. One could do scope tests & software tests to find out what memory accesses are possible... but well, there isn't too much practical use for gaining that info.