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PostPosted: Fri May 10, 2013 12:23 am 
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Well I haven't been very vocal about this project so far, I figure now is the time to spill the beans.

Pretty simple SNES flash cart. Only supports HiROM and LoROM with upper address mapping controlled by the CPLD. It's all new parts so the flash is obviously 3.3v. The CPLD is 5v tolerant, but drives the flash with 3.3v for A12-A22(23). Lower address bits A0-7 and data bus are shifted via a 16x level shifter, the CPLD controls the direction of the data bus through the shifter. Then the few address lines I didn't have room for I used a pair of 4x resistor arrays to level shift appropriately (A8-A11)

It uses Jim's Cool CIC of the SNES flavor. The battery backing is currently similar to NES style using schottky diodes. I might improve upon this, but it's pretty much the simplest solution and can work very well if done properly. If it proves to be a good solution then I'll stick with it long term. If not, I've got some other plans.

It supports up to TWO 8MB flash chips for 16MB total. And it has 128KB of SRAM. So there's quite a bit of room within the Hi-Lo ROM limitations. The CPLD can contain both Hi & Lo rom at the same time and be selectable via the solder jumper on the back to switch back and forth. I have thoughts to configure it for reset selectable multicart form with something like 2x LoROM and 2x HiROM.

It's designed to be programmed via the SNES edge connector. I've modified the Kazzo to support. The side 10-pin connector is for programming the CPLD and CIC, and possibly accelerating the programming speed. The form factor still keeps it fitting in standard original SNES cases. I'm investigating some options to get new SNES cases made up to go along with them. :)

The flash is 90nsec so it should support fast-rom without much trouble.

Right now I'm pretty close to having it working. Got some bugs/kinks to work out as right now only ~90% of the bytes are actually getting programmed on the flash. DKC will actually boot though, has some graphics glitching and then crashes randomly in the title scene. Hoping to have it up and running 100% and order the first batch of boards this month.

I haven't settled on the price yet, it will depend on how much it costs me to have them assembled. My current target is ~$20 for a 8MB version fully assembled. The kazzo is around the same price, so it should make for a simple dev/flash cart setup for under $50.

I'd like to give a special thanks to nocash for his spectacular documentation on the SNES and it's hardware. Because of that I was able to figure out everything I needed without reverse engineering it all for myself.


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PostPosted: Fri May 10, 2013 10:42 am 
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This looks pretty awesome!

Will it be compatible with the Pro Action Replay? No other flash cart is.


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PostPosted: Fri May 10, 2013 11:41 am 
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muckyfingers wrote:
Will it be compatible with the Pro Action Replay? No other flash cart is.


Probably not. I don't know much about how it works, but from what I can assume, I don't have enough hardware to support.

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PostPosted: Fri May 10, 2013 12:23 pm 
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I should post clearer questions, the excitement got the better of me. I was asking if this would work physically on top of the Pro Action Replay.

I didn't mean to make it sound like, "Will the PAR be internally implemented?"

Your answer seems to indicate no either way.


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PostPosted: Fri May 10, 2013 2:19 pm 
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Any chance you'd be willing to release your schematics/verilog? I've been slowly picking away at all of the info out there, as well as PCB scans for the SHVC-1A3M-XX/SHVC-1J3M-XX boards to try to achieve something similar, but with 5V parts (Altera MAX7000 PLD + ST M29F160F), and a hardware schematic would be incredibly helpful. Also, is there any reason your design couldn't be expanded to 32Mb, or is it just because you're using 8Mb ROM chips and adding 2 more would add a lot of tracing complexity? Since I'm using 16Mb chips, that would be less of an issue...


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PostPosted: Fri May 10, 2013 2:31 pm 
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qwertymodo wrote:
because you're using 8Mb ROM chips

infiniteneslives wrote:
It supports up to TWO 8MB flash chips for 16MB total.

picture wrote:
SPANSION S29GL064N90TFI03

You got your bits/bytes backwards. He switched to 3V logic specifically to be able to buy the full size supported.


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PostPosted: Fri May 10, 2013 3:00 pm 
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muckyfingers wrote:
I should post clearer questions, the excitement got the better of me. I was asking if this would work physically on top of the Pro Action Replay.

I didn't mean to make it sound like, "Will the PAR be internally implemented?"

Your answer seems to indicate no either way.


Oh I get ya now, I can't be sure, but I wouldn't be surprised if it DID work with the pro action replay. Logically my cart is pretty much identical to original Hi/LoROM boards. So Unless there is something funky about the PAR that keeps it from accepting 3.3v logic signals I'd guess it'll work.

Any idea why other flash carts don't work with the PAR? I'm guessing because the gui programming interface needs to interact with the flash cart for programming and the PAR gets in the way. If that is indeed the issue with other flash carts then mine is immune to that problem since it's programmed externally.

qwertymodo wrote:
Any chance you'd be willing to release your schematics/verilog? I've been slowly picking away at all of the info out there, as well as PCB scans for the SHVC-1A3M-XX/SHVC-1J3M-XX boards to try to achieve something similar, but with 5V parts (Altera MAX7000 PLD + ST M29F160F), and a hardware schematic would be incredibly helpful. Also, is there any reason your design couldn't be expanded to 32Mb, or is it just because you're using 8Mb ROM chips and adding 2 more would add a lot of tracing complexity? Since I'm using 16Mb chips, that would be less of an issue...

As linariq pointed out you've got your bits/bytes mixed up. MB=megaByte Mb=megabit. I support 16MB * 8(bit per byte) =128Mb, so actually the routing would have been simpler to 'expand' down to 32Mb ;).

I don't really care to fully release the schematic and code. I've pretty much already explained all the details of the schematic in my original post. Converting nocash's docs into verilog is about as simple as programmable logic design gets. It's not that I'm not willing to share/help others, but I'd rather provide feedback as to why your code/schematic is flawed than help someone recreate/debug the design I've already made. You're going to have trouble sticking with 5v logic IMO. If you're having a hard time with schematics of Hi/LoROM then I suggest pulling out a multimeter and probing the board to gain it's schematic vice relying on scans alone.

If you'd like to know specific things about my schematic/code I'm willing to share, I don't want it to be a black box of magic to the user. But ask for something specific vice the enterty of my design.

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PostPosted: Fri May 10, 2013 3:01 pm 
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Unrelatedly: INL, any thoughts about later using BGA for anything? Everything you have fits on one side (save the battery), so toaster oven reflow should be a reasonable plan, and it would dramatically decrease the footprint. (Maybe too much, maybe it'd require a 4 layer board, dunno. That'd probably undo any gains from shrinking them. )


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PostPosted: Fri May 10, 2013 3:07 pm 
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Well the PCB is about as small as it could possibly get while still fitting the form factor of original cases. So unless I have new cases tailored to a smaller PCB there isn't much to gain for board size. These are still fairly simple for toaster oven reflow. I think you're right going to BGA and requiring 4 layers would be a deal breaker. The only thing that would push me to BGA is if I was looking to support something greater than Hi/LoROM to where components became more appealing or were restricted to BGA packaging.

EDIT: Additionally there are significantly smaller package sizes available for things like the CPLD and SRAM without taking the step to BGA. I've considered these, but coarser packages make for easier assembly and I was able to make them all fit so I took the benefit on the assembly side.

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PostPosted: Fri May 10, 2013 4:26 pm 
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infiniteneslives wrote:
As linariq pointed out you've got your bits/bytes mixed up. MB=megaByte Mb=megabit. I support 16MB * 8(bit per byte) =128Mb, so actually the routing would have been simpler to 'expand' down to 32Mb ;).

Oh, wow. Wasn't reading the part numbers closely enough. That definitely changes things.
infiniteneslives wrote:
I don't really care to fully release the schematic and code. I've pretty much already explained all the details of the schematic in my original post. Converting nocash's docs into verilog is about as simple as programmable logic design gets. It's not that I'm not willing to share/help others, but I'd rather provide feedback as to why your code/schematic is flawed than help someone recreate/debug the design I've already made. You're going to have trouble sticking with 5v logic IMO. If you're having a hard time with schematics of Hi/LoROM then I suggest pulling out a multimeter and probing the board to gain it's schematic vice relying on scans alone.
If you'd like to know specific things about my schematic/code I'm willing to share, I don't want it to be a black box of magic to the user. But ask for something specific vice the enterty of my design.

Fair enough, I just tend to make stupid mistakes when converting between text descriptions and schematics, less so comparing schematics visually. But I understand not wanting to release everything, just figured I'd ask. Once I get my schematic finished, I may send it your way to see if I've done anything stupid.


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PostPosted: Fri May 10, 2013 5:36 pm 
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Very cool. =)


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PostPosted: Fri May 10, 2013 7:58 pm 
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Quote:
Oh I get ya now, I can't be sure, but I wouldn't be surprised if it DID work with the pro action replay. Logically my cart is pretty much identical to original Hi/LoROM boards. So Unless there is something funky about the PAR that keeps it from accepting 3.3v logic signals I'd guess it'll work.

Any idea why other flash carts don't work with the PAR? I'm guessing because the gui programming interface needs to interact with the flash cart for programming and the PAR gets in the way. If that is indeed the issue with other flash carts then mine is immune to that problem since it's programmed externally.


I don't know why they don't work with the PAR. From what I've read it's because it patches codes in ram rather than rom and it interferes with way the flash carts load the roms.

Put me down for a set, I would love to test it. Even if it doesn't work with the PAR it is still useful and inexpensive.


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PostPosted: Fri May 10, 2013 10:02 pm 
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I can think of two possibilities wrt the PAR not working with flashcarts, latency or power consumption. I know that the later revisions of the SNES reduced the power supplied to the cart bus to break the Game Genie because the Game Genie drew more power than a cart by itself. If power is the issue, it may work with older revision consoles.


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PostPosted: Fri May 10, 2013 10:37 pm 
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muckyfingers wrote:
I don't know why they don't work with the PAR. From what I've read it's because it patches codes in ram rather than rom and it interferes with way the flash carts load the roms.

Put me down for a set, I would love to test it. Even if it doesn't work with the PAR it is still useful and inexpensive.


That is kinda what I was speculating as to why it doesn't work. Basically most flash carts need to write to ROM for flashing/communicating the game you're trying to play. The PAR was probably never designed for such a crazy newfangled type device. So when the SNES tries to write to cart the PAR prevents those commands from getting to the cart. I shouldn't have that problem, athough I can't be sure it's not something else without fully testing it out. I don't plan to aquire a PAR myself, so I'd be interested in having you test it out for me.

If power consumption is the issue I could be in trouble depending on how sensitive it is. I haven't measured what I'm consuming yet, but those CPLDs can be power hogs depending on how fast/much you've got them switching.

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PostPosted: Sat May 11, 2013 5:15 am 
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If it doesn't handle carts that write to ROM, how does it handle carts that write to SRAM?


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