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PostPosted: Thu Oct 03, 2013 9:05 pm 
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Just FYI, I'm keeping my eye on this thread and will fix these issues, but I'm currently out of the country on vacation. :)


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PostPosted: Sun Oct 06, 2013 9:19 am 
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Revision 1.3 is released: https://dl.dropboxusercontent.com/u/36237540/SNES/jwdonal/schematics/snes_schematic.zip


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PostPosted: Mon Oct 07, 2013 8:26 pm 
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I keep forgetting to mention,

There is a dot to the left of pin 1 (+B) of the RF modulator that shouldn't be there.
No big deal, dead short.

C70 by the newly redrawn DC power jack should actually be C30. On my notes, I had a big ? next to it too. It was only through process of elimination that it's a "3". (There's already a C70 down by the CIC).


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PostPosted: Mon Oct 07, 2013 8:46 pm 
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More great finds! Thanks to everyone for helping me find these errors.

Revision 1.4 is released: https://dl.dropboxusercontent.com/u/36237540/SNES/jwdonal/schematics/snes_schematic.zip


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PostPosted: Thu Oct 10, 2013 12:39 pm 
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So....is pin 9 on WRAM a 'no-connect'?


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PostPosted: Thu Oct 10, 2013 12:42 pm 
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Correct. You can see this in the pinout_s-wram.pdf file.


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PostPosted: Fri Oct 11, 2013 4:47 am 
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Oh I see, I never bothered to look there. I was rather confused that pin 9 was missing from the schematic.


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PostPosted: Sun Feb 23, 2014 11:52 pm 
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Found an eensy typo in v1.3:
The /RESOUT1 line where it goes from below the cartridge slot over towards the S-SMP is erroneously labeled SYSCK.


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PostPosted: Mon Feb 24, 2014 1:11 am 
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Good catch. I found that one and fixed it a awhile ago, but was hoping nobody would notice so that I wouldn't have to release another update. :-P But you got me!

I also fixed the zoom level for the component bookmarks. And I also added a list of all of the nets to the bookmarks.

Version 1.5 is now available.


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PostPosted: Thu May 22, 2014 6:05 am 
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In the process of figuring out why the 2PPU-model of the snes has a blurry picture I've startet to sand mainboards and make hi-res scans of the pcb.
The pal-mainboards seem to be quite a bit different from the ntsc counterparts.
Here's what I have until now, I'll be happy to share any new scans if y'all interested...

You have to click "Download" on the Dropbox-page to get the full resolution image.

SNSP-CPU-01 (PAL) last updated: 05-21-2014 01:00

Bottom with parts:
https://www.dropbox.com/s/rsgakogzt0k9z ... AN_ATV.tif

Bottom stripped:
https://www.dropbox.com/s/8t3mjrxce8jsn ... AN_ATV.tif

Bottom x-ray-vision:
https://www.dropbox.com/s/613mo7gjdilzr ... AN_ATV.tif

Top without parts:
https://www.dropbox.com/s/zpig8vuqfpy1y ... AN_ATV.tif

X-Ray-Vision PhotoShopFile with Layers, aligned (~263MB):
https://www.dropbox.com/s/fuqu94qk6tbbl ... AN_ATV.psd


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PostPosted: Thu May 22, 2014 11:44 am 
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... Is the SNES mainboard four layer? 'cuz I see some unterminated vias around U14 and U8.


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PostPosted: Thu May 22, 2014 1:04 pm 
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I honestly don't know and I always thought it was 2-layers only.
My technical background is limited to soldering and modding consoles.

Could you please mark those vias and post a picture?
Thanks!


edit:
After I reviewed my scan I looked into "snes_schematic_color.pdf" and U14 Pins 1-5 are unterminated, so I guess I did not accidently grind away any traces. Should be fine.
Can anyone confirm this?


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PostPosted: Thu May 22, 2014 4:20 pm 
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I've circled all the isolated vias without any traces touching on the bottom in cyan.


Attachments:
floating-vias.jpg
floating-vias.jpg [ 204 KiB | Viewed 2215 times ]
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PostPosted: Thu May 22, 2014 4:36 pm 
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Ok, thank you!
I only checked those leading to u14 pins 1-5 and the schematic also shows that they lead nowhere...
If you have Photoshop the easiest way to check the leads is just enabling or disabling the top layer which is mirrored to fit the bottom layer.
So, I'm no expert but I'd love to know if my scans can be used or not....
Thanks again!


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PostPosted: Thu May 22, 2014 9:52 pm 
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My thought is that vias can be used for the in-circuit testing, provided the solder resist is kept away from it.

The bed of nails test jig is going to have a coarser clearance spacing around the pogo pins than how close the holes need to be drilled in the actual board. Sometimes a via from the top side just lines up with enough clearance around it, but a lot of time the signal needs to go some distance away and becomes a test point.

If you go looking around some of the clusters of test points, you can pretty much visualize the minimum circular spacing needed around each pogo pin.

edit: For bottom side traces, it's like meh, if a test point can fit, use it instead of a via. Reduces scrap as sometimes vias fail to plate and the rework station will just want to plug a wire in there and solder it on both sides. Can't really get away with that and pass testing if a pogo pin happens to be there.


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