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Legible SNES Schematics
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Author:  lidnariq [ Fri May 23, 2014 12:05 am ]
Post subject:  Re: Legible SNES Schematics

whicker wrote:
My thought is that vias can be used for the in-circuit testing, provided the solder resist is kept away from it.
And verifying, all of the vias I highlighted are without resist.

I just naïvely assumed that the presence of ordinary test pads meant that they wouldn't use vias as test pads.

Author:  Arcade-TV [ Mon May 26, 2014 4:54 pm ]
Post subject:  Re: Legible SNES Schematics

I'll update my scans here from now on:
http://circuit-board.de/forum/index.php ... PCB-Scans/

just stripped an SNSP-1CHIP-02

If anybody has a mainboard to give away for this purpose please contact me, thanks!

Author:  caitsith2 [ Fri May 30, 2014 3:10 am ]
Post subject:  Re: Legible SNES Schematics

One thing to do, after the scans, is to etch away the copper layers on the top and bottom, then shine a light through the board. If there is more than 2 layers, the copper in the middle layers will block the light where ever it is present. On the other hand, this will also confirm it being 2 layers, if the only thing you see is vias in the board after etching away the top and bottom copper.

Author:  Ramsis [ Mon Feb 29, 2016 2:16 pm ]
Post subject:  Re: Legible SNES Schematics

@jwdonal, great work, highly appreciated! :D

I think I've found an error in v1.5 though. VS and GND on the LM324 seem to be reversed (cf the datasheet):

Attachments:
lm324.png
lm324.png [ 64.67 KiB | Viewed 2993 times ]

Author:  jwdonal [ Mon Mar 07, 2016 11:19 pm ]
Post subject:  Re: Legible SNES Schematics

Thank you much for the bug report. It appears that you are indeed correct. I will make a note of this to fix in a future revision. Regenerating the whole set of files for this one change would be a bit overkill. But it will definitely get fixed in the next revision. Thanks!

Author:  ikari_01 [ Thu May 05, 2016 4:14 pm ]
Post subject:  Re: Legible SNES Schematics

/RESET is marked an output (to signal /RESOUT1) on S-DSP. Is this correct? It is usually controlled by PPU2 and the POR IC.

Author:  tepples [ Thu May 05, 2016 5:00 pm ]
Post subject:  Re: Legible SNES Schematics

As I understand it, /RESET on the Super NES is like an /IRQ pin in that it's open drain. This means it's pulled up to +5 V through a resistor (on the order of 100 kΩ), but any IC connected to that line can output 0 V to assert it. The lock CIC in the console pulls it low until the RNGs synchronize, but the cart can also pull it low if it wants to, say, force the S-SMP back into its bootloader for a flash cart's SPC loader.

Author:  ikari_01 [ Thu May 05, 2016 5:03 pm ]
Post subject:  Re: Legible SNES Schematics

Of course, the sd2snes does it too. But can the S-DSP?

Author:  tepples [ Thu May 05, 2016 5:11 pm ]
Post subject:  Re: Legible SNES Schematics

Perhaps there's some vestigial "watchdog" feature in the S-DSP that resets the system if the S-SMP doesn't make any S-DSP accesses for an extended period. I don't know what enables it; we might need to decap and photograph the S-DSP, just as the RP2A03G's test mode was discovered through a microphotography job.

Author:  whicker [ Thu May 05, 2016 6:54 pm ]
Post subject:  Re: Legible SNES Schematics

I doubt it is an output and probably a schematic error, although it might actively drive itself low for the duration of its internal reset if it is open drain, but that still doesn't count.

On the old schematic it's just called \POR and there are no directional arrows.
POR = "Power-On Reset" (probably)


I suppose the better question to ask is: Does the S-DSP have some undocumented register that writing to it causes it to blip the reset pin? probably not.

Author:  jwdonal [ Sat Sep 17, 2016 9:17 pm ]
Post subject:  Re: Legible SNES Schematics

Someone has asked me a question regarding the signal connections to the S-WRAM and I can't figure out the answer. I think it might be an error on the schematic but can find no evidence as such.

The question is: Why is S-CPU address bit 22 (i.e. CA22) connected to the "ENA" pin of the S-WRAM?

First, there is an underlying assumption within the question that the "ENA" pin of the S-WRAM "enables" the WRAM to function. Specifically, unless the ENA pin is asserted (i.e. logic high) then the WRAM will neither honor writes to its memory nor will it respond with (i.e. drive) valid data onto the data bus when it is read. Another way of saying this is that the ENA pin acts as another chip-select (CS) pin (of which the WRAM already has 6 others).

Second, there is another assumption that the ENA signal is active-high. This may or may not be the case, but even if it is active-low the question still needs to be answered.

The memory map for the SNES is given in Anomie's memmap.txt as follows:
Code:
  Banks  |  Addresses  | Speed | Mapping
---------+-------------+-------+---------
 $00-$3F | $0000-$1FFF | Slow  | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
         | <.......snip......> |
         | $8000-$FFFF | Slow  | Address Bus A + /CART
---------+-------------+-------+---------
 $40-$7D | $0000-$FFFF | Slow  | Address Bus A + /CART
---------+-------------+-------+---------
 $7E-$7F | $0000-$FFFF | Slow  | Address Bus A + /WRAM
---------+-------------+-------+---------
 $80-$BF | $0000-$1FFF | Slow  | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
         | <.......snip......> |
         | $8000-$FFFF | Note2 | Address Bus A + /CART
---------+-------------+-------+---------
 $C0-$FF | $0000-$FFFF | Note2 | Address Bus A + /CART

Relating the above memory map with the assumption regarding the "ENA" pin's behavior this doesn't seem to make any sense. Specifically, if the WRAM only functions if CA22 is asserted, then that means it will only respond to read/write requests on banks $40-$7F and $C0-$FF (this covers the $7E-$7F WRAM region). But this doesn't match the above mapping because WRAM clearly does respond in banks $00-$3F and $80-$BF.

Similarly, if we say that ENA is really an active-low signal, then WRAM would only respond to read/write requests on banks $00-$3F and $80-$BF but _not_ on banks $7E-$7F.

I'm thinking one of three things is going on:
1) It's not really CA22 that's connected, it's actually some other address bit (although this would mean that multiple documents and other schematics that I've found are also wrong).
2) The assumed behavior of the "ENA" signal is totally wrong (although I can't really think of any other possible meaning for a signal with an "ENA" abbreviation)
3) I'm being an idiot and missing something painfully obvious (quite possible)

Does anyone have any insight on this?

I'd love to correct the schematic and release an update if it's a mistake.

Author:  nocash [ Sat Sep 17, 2016 9:29 pm ]
Post subject:  Re: Legible SNES Schematics

The chipselect is the /RAMSEL signal. And ENA is simply selecting the addressing mode, either a small chunk (in bank 0-3Fh, with A22=0, and several address lines ignored (particulary A16)) or a large chunk (in bank 7Eh-7Fh, with A22=1, and all connected address lines used).

Author:  jwdonal [ Sat Sep 17, 2016 10:46 pm ]
Post subject:  Re: Legible SNES Schematics

Nocash is the man!! This is very valuable information. Thanks! :D

Out of curiosity......how the heck did you figure that out?

And sorry if I missed that info in your fullsnes.txt...I searched (case-insensitive) for every occurrence of "wram" and didn't see anything in regards to what the ENA pin did (only that it was connected to CA22).

Author:  nocash [ Sun Sep 18, 2016 6:24 am ]
Post subject:  Re: Legible SNES Schematics

jwdonal wrote:
how the heck did you figure that out?

Basically, by looking at your schematic. And then wondering about the differences between 7Eh-7Fh:0000h-FFFFh (whole 128K address range with mask 1FFFFh) and 00h-3Fh:0000h-1FFFh (first 8K range with mask 01FFFh (or mask 0FFFFh might also work since A13-A15 are already/always zero in that wram area, but A16 must be masked off in bank 01h,03h,05h,etc)). So ENA must stand for "EnableAddress" or "EnableA16" or the like.

Author:  jwdonal [ Sun Sep 18, 2016 10:10 am ]
Post subject:  Re: Legible SNES Schematics

nocash wrote:
jwdonal wrote:
how the heck did you figure that out?
Basically, by looking at your schematic.
I LOL'd hard at this. XD
nocash wrote:
And then wondering about the differences between 7Eh-7Fh:0000h-FFFFh (whole 128K address range with mask 1FFFFh) and 00h-3Fh:0000h-1FFFh (first 8K range with mask 01FFFh (or mask 0FFFFh might also work since A13-A15 are already/always zero in that wram area, but A16 must be masked off in bank 01h,03h,05h,etc)).
Cool, I never would have thought of that.
nocash wrote:
So ENA must stand for "EnableAddress" or "EnableA16" or the like.
Aha! Nice.

Thanks again for the info. :)

UPDATE: I added this pin description to the S-WRAM part pinout. So it will be included in the next release.

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