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PostPosted: Fri Oct 18, 2013 2:15 pm 
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On a 64K sram chip there is a /CS1 and a CS2 pin. On a regular SNES cart the CS2 pin on the sram is tied to MAD-1 pin 9 which then ties to /RESET. On checking the only 256K sram cart I own which is Mario Paint, it doesn't use the MAD-1 chip and there's no CS2 pin on the sram...

What is the purpose of the second Chip Enable on 64K sram? Why is it that a 64K sram chip has 2 enables but a 256K sram only has 1?

For reference, I was comparing these 2 chips:

http://www.buyicnow.com/files/datasheet/STATIC_RAM/348.pdf -------64K sram

and

http://www.mouser.com/ds/2/198/62-65C256AL-258444.pdf ---------256K sram


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PostPosted: Fri Oct 18, 2013 2:17 pm 
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No-one ever made 26 pin packages; They only had 24 and 28 pin packages. So either the extra pins were going to do nothing at all, or they decided it'd be more useful to give people more flexibility in how they enabled talking to the RAM.

Larger RAMs required more address lines, so there was no longer any room for an extra enable.

the MAD-1 there is serving as extra memory protection against spurious writes by the CPU on powerup and powerdown.


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PostPosted: Sat Oct 19, 2013 12:27 am 
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CS2 is sometimes called /RST, and is typically tied to Vcc through a pull-up resistor. If that doesn't make sense, the / means active-low, so it's either an active-high chip enable (chip is enabled when the pin is high) or active-low reset (chip is reset when the pin is low... which means the pin has to be high in order to enable the chip). It's usually used as a power-good enable, and isn't typically used in the same way you typically use /CS. /CS is used to control the R/W functions, and the CS2 is just used to disable the chip if the power drops out.


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PostPosted: Sat Oct 19, 2013 1:12 am 
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Just to make sure it's clear: the SRAM itself cares about +CS and /CS the exact same amount. +CS must be Vcc and /CS must be ground in order to talk to the SRAM. Only the context varies. For example, a fictional 6502-based machine could connect A15 to /CS and M2 to +CS to map and mirror the 8KiB RAM across the entire bottom 32KiB of the 6502's address space. Similarly, on the NES the MMC1 controls I/O to PRG RAM on pertinent boards using the +CS line, not the /CS line. (SNROM connects /CS to CHR A16. Other SxROM boards connect /CS to ground)


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PostPosted: Sat Oct 19, 2013 3:15 pm 
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Yeah, what lidnariq said. Sorry if I made it sound otherwise, but the chip enable logic requires that /CE1 be low and CE2 be high. If either of those conditions is not met, the chip is disabled. I was merely commenting on the way that I have, in my own personal experience, seen CE2 used most commonly, as well as explaining why CE2 is sometimes labeled as /RST instead (you often see it tied to a system-wide POR reset signal).


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PostPosted: Sun Oct 20, 2013 1:38 pm 
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That clears things up a bit, thanks guys!


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