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PostPosted: Sat Oct 12, 2013 11:27 pm 
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The Anomie/Blargg spc700cyc.txt states that all branch instructions are either 2 or 4 cycles (2 if branch not taken, 4 if branch taken). However, is it really always 4 cycles if the branch is taken? Or is it 3 cycles if the branch is taken within same page and only the max 4 cycles if the branch is taken to a different page?
The latter makes a lot more sense to me and would be consistent with other processors that I'm familiar with.


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PostPosted: Sun Oct 13, 2013 12:34 pm 
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It probably chooses to have a consistent branch-taken time rather than inconsistency for an extra cycle on non-page-crossing cases.

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[4 only on page crossing] makes a lot more sense to me and would be consistent with other processors that I'm familiar with.

I thought that the 6502 was the only processor to do this. I don't know of any others.


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PostPosted: Sun Oct 13, 2013 1:44 pm 
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Thanks for the answer Blargg.
blargg wrote:
I thought that the 6502 was the only processor to do this. I don't know of any others.
I thought that both the 6502 and 65816 both did this, but apparently the 65816 only does this when in "6502 emulation mode". So yeah, I guess just the 6502.


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PostPosted: Sun Oct 13, 2013 5:24 pm 
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Incorrect. The 65816 adds 1 cycle to branch operations if the branch is taken, regardless if e=1 (emulation mode) or e=0 (native mode). The 6502/65c02 operates the same way.

THIS part only applies to the 6502/65c02 (and thus 65816 when e=1): if the branch crosses a page boundary the CPU adds 1 cycle.

There are other conditions where cycles are added on the 65816 when e=0 too, which I will not list off here because it's besides the point and you can look them up yourself. :-)

If you want reference materials for all of my statements, please refer to Programming the 65816 (including the 6502, 65C02, and 65802) by Western Design Center -- refer to Chapter 18 (PDF page 327 onward) in its entirety depending on what opcodes you care about (see the little "mini-chart" per opcode).

TL;DR -- the 65816 with e=1 behaves exactly like a 65c02 (e.g. the jmp ($xxff) bug does not happen on a 65816 with e=1).


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PostPosted: Sun Oct 13, 2013 5:45 pm 
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The focus was on an extra cycle for page crossing, not extra time on branch taken (which virtually every processor does):
jwdonal wrote:
[...] is it really always 4 cycles if the branch is taken? Or is it 3 cycles if the branch is taken within same page and only the max 4 cycles if the branch is taken to a different page? The latter makes a lot more sense to me and would be consistent with other processors that I'm familiar with.


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PostPosted: Tue Oct 15, 2013 5:36 pm 
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jwdonal wrote:
The Anomie/Blargg spc700cyc.txt states that all branch instructions are either 2 or 4 cycles (2 if branch not taken, 4 if branch taken).

Yup, that info is correct. The SPC700 doesn't need extra cycles when crossing page boundaries.


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