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 Post subject: SPC700 STOP instruction
PostPosted: Thu Oct 31, 2013 12:25 am 
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Joined: Sat Jun 27, 2009 11:05 pm
Posts: 719
Location: New Mexico, USA

Above is a screenshot of the SPC700 executing the STOP instruction. The first cycle occurs on the falling edge of CPUK marked with Cursor 1. The second cycle is on the falling edge marked with cursor 2. In the final cycle the instruction has completed.

A couple very interesting things to note.

1) Once STOP has executed the PD3 signal flatlines.
2) Once PD3 flatlines, CPUK from the DSP chip changes both period and duty cycle (in fact, it exactly halves its frequency (to 1.024MHz) and changes from 50% duty cycle to 75% duty cycle.

It would appear that CPUK from the DSP is affected by the behavior of PD3. In addition, I was originally thinking that PD3 was driven by the DSP but it seems that it's actually driven by the SMP since it flatlines as soon as STOP is executed.

PD3 flatlining doesn't really bother me that much since I always thought of it as a clock-enable for the SMP for the purposes of generating the effective 1.024MHz internal clock rate. And this clock-enable could be driven by either the DSP or SMP - it doesn't really matter which one.

However, the CPUK signal changing as a result of PD3 flatlining is extremely odd - I don't understand why that would happen. The other weird thing is that, prior to the system reset being released, CPUK is operating at its normal 2.048MHz @ 50% duty cycle and the PD3 signal is _flatlined_. So PD3 affects CPUK..........but only after reset is released?? I mean, that's certainly possible, but why? Here is a screenshot of RESETx being released after power-up (see the Trigger cursor).

Anyone have any thoughts?

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