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 Post subject: Re: HDMI SNES?
PostPosted: Sun Dec 11, 2016 6:16 pm 
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Location: NE Indiana, USA (NTSC)
148.5 MHz is presumably for 1920x1080 including blanking: 2200*1125*60. But you'll probably have to slightly slow down the Super NES clock as well, as the S-PPU normally outputs 60.1 Hz, not 60.0 Hz that the HDMI spec expects.

  • Most games use double strike mode, which renders 262 lines of 1364 cycles, minus four master clocks every two frames, for an average of 357366 cycles per frame. To run it at exactly 60 Hz, you need to clock it at 21441960 Hz.
  • RPM Racing and a couple others use interlace mode, which renders 262.5 lines of 1364 cycles, with no short lines, or 358050 cycles per field. To run it at 60 Hz, you need to clock it at 21483000 Hz.
  • The PPU switches between 224-line and 239-line modes by moving the vsync pulse and holding start of picture constant, not by moving the start of picture and holding vsync constant. When a game switches between the two, you'll need to speed up or slow down the CPU and PPU until it's synced up again.

And you'll need to use a circular buffer to collect video lines. A single-line buffer (as would be used for a 240 to 480 line doubler) doesn't work for 720 or 1080, as 240 lines out of 262 is a smaller fraction than 1080 out of 1125.

So the basic architecture would look like this:

frequency synthesizer -> CPU and PPU -> ADC for RGB channels -> circular buffer -> upscaler -> HDMI muxer
analog audio from cartridge (such as Super Game Boy or MSU-1) -> ADC at 48 kHz
24 MHz frequency synthesizer -> APU -> upsample from 32 to 48 kHz -> add to cart audio -> HDMI muxer


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 Post subject: Re: HDMI SNES?
PostPosted: Sun Dec 11, 2016 9:34 pm 
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Joined: Wed Nov 30, 2016 9:59 pm
Posts: 54
tepples wrote:
148.5 MHz is presumably for 1920x1080 including blanking: 2200*1125*60. But you'll probably have to slightly slow down the Super NES clock as well, as the S-PPU normally outputs 60.1 Hz, not 60.0 Hz that the HDMI spec expects.

  • Most games use double strike mode, which renders 262 lines of 1364 cycles, minus four master clocks every two frames, for an average of 357366 cycles per frame. To run it at exactly 60 Hz, you need to clock it at 21441960 Hz.
  • RPM Racing and a couple others use interlace mode, which renders 262.5 lines of 1364 cycles, with no short lines, or 358050 cycles per field. To run it at 60 Hz, you need to clock it at 21483000 Hz.
  • The PPU switches between 224-line and 239-line modes by moving the vsync pulse and holding start of picture constant, not by moving the start of picture and holding vsync constant. When a game switches between the two, you'll need to speed up or slow down the CPU and PPU until it's synced up again.

And you'll need to use a circular buffer to collect video lines. A single-line buffer (as would be used for a 240 to 480 line doubler) doesn't work for 720 or 1080, as 240 lines out of 262 is a smaller fraction than 1080 out of 1125.

So the basic architecture would look like this:

frequency synthesizer -> CPU and PPU -> ADC for RGB channels -> circular buffer -> upscaler -> HDMI muxer
analog audio from cartridge (such as Super Game Boy or MSU-1) -> ADC at 48 kHz
24 MHz frequency synthesizer -> APU -> upsample from 32 to 48 kHz -> add to cart audio -> HDMI muxer


Here's a thing I've been wondering. If the people working on FPGA's are working on PPU1 and PPU2 separately, and PPU2 is the only thing that is outputting the signal that goes to S-ENC, would it be possible to re-implement just PPU2 using known aspect ratio sizes?
eg 1-20x multipliers. 1080 is the only one that doesn't wouldn't work for pixel perfect, but presumably you'd want to either 4X it and live with the windowbox or 5X and crop it to 216 pixels (1080) or leave it at 1200 for WUXGA. 480 is 2x, 720 is 3x, 5X WUXGA, 9x UHD (4K), and 18X SUHD (8K)

Like, I don't think we are anywhere near that right now. A really blunt version of this would making PPU2's for 240,480,720,1080,2160,4320 if the logic in it is little more than "here's a map, copy the numbered tiles I already put in the VRAM treasure chest here" maybe it's only hardwired to do 240p and it's literately fitting it into other resolutions (what does it do on PAL?) One of those is the hires mode, yet 240 output. When I saw the field line in the pinout I was like "looks like maybe it supports telling the PPU2 to alternate between interlaced fields."

And as mentioned elsewhere, HDMI can be driven by a FPGA directly, which is essentially what they did for both FPGA NES systems from what I've seen and not a separate HDMI chip which IIRC requires an entire framebuffer and that's the reason for latency. A lot of other FPGA versions of 8 and 16-bit computers have run into a similar problem where they can't output a full color VGA signal over their FGPA board's VGA, but can't output >480p HDMI because they used low-cost FPGA's that don't have enough memory for the line buffer.

I might be wrong, but I would really like to see something, and up until late last month it seemed like nobody was working to save the SNES from going extinct. I keep looking at the price of the FPGA Dev boards and am I like "where am I going to hook up a real cart on this?" and "exactly how big of FPGA is needed?" I have to wonder where these clone systems get their cart and controller connectors from.

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