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PostPosted: Sun Oct 02, 2016 5:05 pm 
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I never thought about this before, and I guess I'm lucky I haven't ran into any problems yet, but if I'm not mistaken, STZ doesn't actually affect the accumulator, does it? By that same token, the size of the accumulator shouldn't affect this instruction, should it?

I also got to thinking, does INC affect the whole accumulator, or only what the accumulator is set to? The only reason I'm asking this is that "C" represents the whole 16 bits like TCD, but here, I imagine it's just an abbreviation for increment.


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PostPosted: Sun Oct 02, 2016 5:14 pm 
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stz is affected by the size of the accumulator (i.e. it writes $0000 if m=0 (16-bit), or writes $00 if m=1 (8-bit)).

Yes, inc (e.g. inc a) obviously affects the accumulator, thus whether m=0 or m=1 affects what happens when you do inc. Written in code, to make this point crystal clear:

Code:
rep #$20
lda #$12ff
sep #$20
inc
; Accumulator now holds $1200 ($ff+1 = $00 ($ff wrapped to $00); upper byte is
; left alone because at the time of the increment, m=1).

rep #$20
lda #$12ff
inc
; Accumulator now holds $1300 ($12ff+1 = $1300).

**All** of this is fully/clearly documented in the WDC 65816 documentation, Chapter 18 (Instruction Set).


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PostPosted: Sun Oct 02, 2016 5:30 pm 
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The reason's it's referred to as the "M" bit is because it affects the size of Memory operations (as well as the "accumulator" ;) )

Basically, if a given instruction could possibly support either 8 or 16-bit operands, and it's not controlled by the "X" bit, it's controlled by the "M" bit.


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PostPosted: Sun Oct 02, 2016 5:37 pm 
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The m flag also affects incrementing and decrementing memory directly.
Code:
rep #$20        ; set m to 16-bit
lda #$10ff
sta $00         ; $00 = #$ff, $01 = #$10
inc $00         ; $00 = #$00, $01 = #$11

rep #$20        ; set m to 16-bit
lda #$10ff
sta $00         ; $00 = #$ff, $01 = #$10
sep #$20        ; set m to 8-bit
inc $00         ; $00 = #$00, $01 = #$10

This, along with stz, is why the full name of m is "Memory/Accumulator Select", and why it's m rather than a.


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PostPosted: Mon Oct 03, 2016 6:00 pm 
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STZ is basically a smaller version of this 6502 code:

Code:
LDA #0
STA RAM_Label


When 16-bit, it equates to this 6502 code:

Code:
LDA #0
STA RAM_Label
STA RAM_Label+1


About A vs. X and Y:

A is sized depending on the M (Memory) bit, X and Y are sized via I (Index) bit, the CPU combines X and Y size bits temporarily in the I bit and therefore since the 65816's CPU manipulation/flag bits (which are set depending on opcode type) is only 8 bits, the result instead of three bits, there's two bits to use SEP and REP on,

So think of M (as in A) as a main program register, and I (as in X and Y) as your auxiliry program register(s)!

EDIT: Cleaned up, and added some missing info, and added proper stuff about the CPU manipulation (opcode flag) bits from the processors

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Last edited by Hamtaro126 on Sun Oct 09, 2016 3:57 am, edited 3 times in total.

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PostPosted: Tue Oct 04, 2016 10:28 am 
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Hamtaro126 wrote:
X and Y are actually split from the giant I register (meaning Index) and therefore instead of three regs, there's two regs to use SEP and REP on,


This is pretty misleading; are you just making this up to try to explain why there's only one size flag for both index registers?

X and Y are totally physically separate and also have different behavior for indirect addressing (i.e. they aren't interchangeable). I think the only real reason there's one flag is because anything else would have just complicated things from both a hardware and software design standpoint (and there weren't enough available bits in the 8-bit status register anyway, so how would you do it?)


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PostPosted: Sun Oct 09, 2016 3:44 am 
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@Renevant: You are actually correct, I was actually meaning to say "X" and "Y" are still seperate registers, but the "I" bit (in a visual sense) sets up a temporary combination of "X" and "Y" bit registers due to the 6502-family CPUs having only 8 processor manipulation bits.

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