I'm really excited to finally share this with you. I've been working on implementing the SNES in an FPGA using Verilog HDL. In the past I've implemented an NES, SNES APU, HQ2X filter, etc in an FPGA so I figured full SNES was the next logical step. I've been making lots of progress and I wanted to share with you all the current state of the design.
Forum ate my original post.
I'm looking forward to this. Do you know how many logic units are currently used on the parts you've emulated so far? When complete would it fit on the MIST board (a board for emulating 16-bit game consoles/computers on a FPGA) or would it require a Cyclone IV or V board?
I think from a legal perspective I believe you're actually in the clear for everything but the PPU and CIC. The PPU doesn't contain any firmware, so as long as you haven't used any illegal information (eg leaked developer documentation) it should be fine. The PPU you make likely would work as about as good as the version of the SNES you captured data from (There are apparently two CPU's and three PPU2's according to console5 before considering the 1-chip.) The CIC is just a question of not copying the CIC firmware since Nintendo has won that battle before with the NES.
What I think should happen is if you open-source the CPU and SPC parts, there are existing open source cores for these out there already so it's worth knowing you produced accurate cores specifically designed for the SFC/SNES. I'd suggest adding a CPUID function in each core if that is viable. The PPU's I think isn't problematic so much as if you release individual FPGA versions of the chips, ASIC's could be produced.
But as for if clones would use them, I actually don't think they would. The Clones are in the market for people to play the games, they don't seem to care if they're accurate (or even last very long,) so things like the Retron 5 (a 50Mhz xilinx spartan xc3s50 FPGA and a 1.6Ghz Rockchip 3066 ARM Cortex-A9 ) and the RetroFreak (Two ARM chips , a 50Mhz nuvoton nuc220ve3an and a 1.6Ghz Rockchip 3066 ARM Cortex-A9 ) are just software emulators now. They apparently use SNES9x as their Super Nintendo emulators. The previous generation (Retro N and similar) basically just had ASIC clones. So they're not producing those anymore, and I'm not sure if that's because the parts aren't available, or if it's cheaper to just use an emulator on the ARM chip. This may be what the 50Mhz FPGA is for on Retron 5, to trick the CIC chip so that the ROM can be read. I don't own these devices, I just looked at PCB photos.
What I think there is a market for, is a high-quality FPGA-SNES Development board (with USB-C/HDMI/MHL connections for power/video) that can also be used to replace existing dead SNES PCB's with 3D printed new shells for those that are off-colored (or SFC shells that take SNES carts for those that never liked the SNES design.) I'm fairly certain there is at least enough people out there (I think you'd need at least 1000 to justify creating boards) that such a thing if it could be created for under $200 would justify the cost of producing it. Otherwise the alternative is just providing the necessary source (eg on Opencores) and just see if it grows legs and someone does it anyway. You'd want a way to at least identify what devices are made with it just so that if it's successful it can be identified from an original SNES.
The thing I'd do (just to "one more thing" any potential creditless-clones) is to implement a setup screen when no cartridge is inserted that shows what version of the FPGA source/chips is used.
But just to roll back a sec, I think for a HDMI output, there would need to be a HDMI-resolution aware PPU. VGA is fine when there are still monitors that support it, but 4K monitors do not (and we're rapidly seeing monitors with only DisplayPort/HDMI2/MHL.) The lowest resolution most HD and 4K monitors support is 640x480 which isn't a great fit for the SNES, but a 4K monitor needs a 9X multiplier , and scaling is much faster done in an ASIC on the fly than than it is running it through a pseudo S-ENC that does scaleing from the generated 240p since there is a HiRes mode that has more resolution. So I don't know if this would require a parallel PPU that performs a 1-20x scale on a pseudo-framebuffer or just copies all the draw commands using a tilemap that is scaled by the required size. At any rate this is just in the vein of "future-proofing as much as possible" since a conventional scalers in televisions/monitors tend to add too much latency and fuzziness (designed for VHS video, not video games.) TV manufacturers don't really care to test for supporting video games funny enough.
For audio, the one complication that HDMI adds is that any audio connected to the cartridge or expansion slot would need to be re-encoded digitally unless there is a way to emulate the chip that is generating the audio. So that might be an interesting thing to try for a FPGA-SNES development board, otherwise an ADC process would be required for the audio, and probably oversampling it to 48 or 96khz (32khz x3) for HDMI. 32Khz apparently might work with HDMI but hardware support is poor. Past a certain point, some things are overkill.
I'm looking forward to seeing what jwdonal produces. I recently decided to try and fix a few SNES systems and if it were possible to just create new PCB's that work with current generation TV's I think more people would be interested in just being able to play the games they have at whatever price. (The Retro N 5 and RetroFreak are just software emulators, hence the cheap price.) I'd be more than willing to figure out how to setup my own FPGA to try this, but there's not quite enough detail to know what FPGA's would work, and without a way to use it on a 4K monitor with HDMI2.0/DisplayPort/MHL connection, that means either letting the monitor scale it, or digging out a working CRT.