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PostPosted: Mon Jan 23, 2017 2:35 am 
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jwdonal wrote:
Performance enhancements would certainly be possible since the hardware is fully programmable but the real question is what games would use them? The answer is none - at least not any official ones anyway. So while it's a cool thing to think about, there would really be no point in doing it.


That's not exactly true: Treasure Hunter G has a DMA queue which allows some DMA transfers be delayed to next NMI if there is no more VBlank time left. If DMA could execute faster than the original SNES, then we could measure improves in all games than implements such a queue (I guess THG isn't the only one).
And the same with FIFO-buffered accesses to $2140/41/42 to send samples to APU. Most games use this scheme to send samples, so buffering acceses could reduce the latency to the most: each time SNES CPU puts a byte into $2140, it is buffered so it is acknowledged inmediately from the APU (FIFO) side. This, again, reduces CPU load and increased performance could be measured.

Besides, it could be used for new homebrew development, which would be nice :D


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PostPosted: Mon Jan 23, 2017 3:03 am 
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Interesting... didn't know about those.

Certainly for some games that are horribly slow, like StarFox for example, some performance improvements that could be optionally enabled/disabled would be worth looking into.


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PostPosted: Sun Feb 05, 2017 12:10 am 
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Next progress update.

Mode 7...'nuff said. ;)

https://youtu.be/c8r58jAwWRw


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PostPosted: Thu Feb 09, 2017 3:21 am 
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Question?

Since the 65816 doesn't have the NMOS vs CMOS issues we have on other devices and the SNES uses a stock 65816. Why not just use a modern 65816 chip they you can get for $9 from WDC, and free up space on the FPGA, or shrink the FPGA to save costs? You might be able to fit two 65816s on the board and then put the SA-1 extras in the gap in the FPGA to emulate the SA-1 modes.


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PostPosted: Thu Feb 09, 2017 4:03 am 
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Oziphantom wrote:
Question?

Since the 65816 doesn't have the NMOS vs CMOS issues we have on other devices and the SNES uses a stock 65816. Why not just use a modern 65816 chip they you can get for $9 from WDC, and free up space on the FPGA, or shrink the FPGA to save costs? You might be able to fit two 65816s on the board and then put the SA-1 extras in the gap in the FPGA to emulate the SA-1 modes.


I suspect it's a combination of:
1. That defeats the purpose of emulating it accurately (what bugs may have been fixed in a new core?, What bugs need to exist?)
2. Voltage issues.
3. If you license the actual CPU core used in the SNES, you make the project's legality questionable since licensed cores can't be redistributed (NDA contract and all.) At least one previous FPGA-SNES attempt by another party used licensed a WDC core.
(All patents on SNES hardware should have expired between 2011 and 2014)

But for now he's developing it on a $600 FPGA development board. If at some point someone wants to try building a SNES using a mixture of old and new parts, they could try that, but you're basically looking at multiple problems that need to be solved before it even gets there, that's why it makes more sense to just build the CPU core to spec in the first place on the FPGA.

There are different goals when you want to emulate the device accurately, versus cheaply. Cheap is why you get clones that damage your cartridges and don't work with expansion chip games.

* The SNES has some kind of memory-mapped multiply-divide, which means that likely complicates using an off-the-shelf 65816, but someone who actually knows how it works would know better

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PostPosted: Thu Feb 09, 2017 6:50 am 
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It wouldn't matter, as the Super NES also has a DMA unit. Both are memory mapped I/O, and both would need to be in a custom memory controller in any clone, whether the 65816 is integrated or not.


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PostPosted: Thu Feb 09, 2017 11:12 pm 
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Yeah, the S-CPU has a lot of custom stuff on it. I assume you could mod a standard 65816 into a 5A22 via FPGA wizardry, but it seems like it might be better to just do the whole thing on the FPGA.


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PostPosted: Fri Feb 10, 2017 6:50 am 
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The extra stuff is analogous to a memory controller hub. I agree that it's probably more convenient when assembling the system to put everything, including the 65816, into the FPGA. But assuming compatible voltages, you can use a discrete 65816 during development and then just reimplement the memory controller part in the FPGA until you finish cloning the 65816.


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PostPosted: Sun Feb 19, 2017 5:32 pm 
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A strange new source file for the VeriSNES just appeared on my computer...what on Earth could it mean?? :lol:
Attachment:
spr_fetch.PNG
spr_fetch.PNG [ 1.71 KiB | Viewed 1217 times ]


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PostPosted: Sun Feb 19, 2017 6:29 pm 
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jwdonal wrote:
A strange new source file for the VeriSNES just appeared on my computer...what on Earth could it mean?? :lol:
Attachment:
spr_fetch.PNG

You programmed it up in a coke-induced frenzy, passed out on the keyboard, and you don't remember a bit of it this morning? :D

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PostPosted: Sun Feb 19, 2017 9:06 pm 
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I guess Coke makes Sprite in more than one way.

Image
330 mL
- Photo by Emilian Robert Vicol


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PostPosted: Sun Feb 19, 2017 10:21 pm 
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jwdonal wrote:
A strange new source file for the VeriSNES just appeared on my computer...what on Earth could it mean?? :lol:
Attachment:
spr_fetch.PNG

Honestly, I have no idea why you're so excited about adding lemon-lime flavored soft drinks into your FPGA SNES.

7-Up just makes no sense to put on an FPGA.


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PostPosted: Sun Feb 19, 2017 10:24 pm 
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syboxez wrote:
7-Up just makes no sense to put on an FPGA.
They wanted to experiment with bubble memory.

(I'll see myself out)


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PostPosted: Sun Feb 19, 2017 10:49 pm 
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syboxez wrote:
7-Up just makes no sense to put on an FPGA.

Image
David Perry disagreed


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PostPosted: Mon Feb 20, 2017 10:48 am 
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jwdonal wrote:
A strange new source file for the VeriSNES just appeared on my computer...what on Earth could it mean?? :lol:
Attachment:
spr_fetch.PNG


Pun aside, I'm guessing you have a new routine that fetches the sprite data from VRAM and OAM to hardware timing standards (at least what you could measure).


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