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PostPosted: Thu Feb 09, 2017 3:43 pm 
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Hi, quick question as I am reading through the SNES graphics documentation -- mostly Qwertie's found here: https://emu-docs.org/Super%20NES/General/snesdoc.html.

This is pretty vague to me as I haven't found a clear answer to this...

When Qwertie refers to "register $2121" for example, does he just mean the address in memory at $2121? In the SNES are registers other than the main 65816 registers referred to addresses in memory?

Also I am confused as to what $2121 is in CG RAM. The reference says: Address for accessing CGRAM. With the description: This register selects the word location (byte address * 2) to begin uploading (or downloading) data to CGRAM.

I am confused because in most demo programs, $2121 gets loaded with 0. So what does this mean?

Thanks all.


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PostPosted: Thu Feb 09, 2017 3:50 pm 
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A lot of articles use "register" to mean an MMIO port.

Programs write a value $00 to $2121 (CGRAM address port) to tell the S-PPU that they're about to write palette entries starting at color $00 (the beginning). If a program instead wanted to write palette entries starting at color $80 (first sprite palette), it would instead write $80 to $2121.

It's the same reason that programs might write $3F then $00 to address $2006 (VRAM/CGRAM address port) on the NES PPU, $0000 to address $0402 on the TurboGrafx-16 VCE, $C0000000 to address $00C00004 (control port) on the Genesis VDP, or $00 to port $3C8 on the VGA. For which other retro platforms have you programmed, if any?


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PostPosted: Thu Feb 09, 2017 3:59 pm 
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Ah so basically, these registers refer to the locations in memory to the device? That is in this case the SNES's PPU?

Does that mean then the addresses written to these registers are the addresses on the system memory side? In this case the SNES main RAM?


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PostPosted: Thu Feb 09, 2017 4:11 pm 
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Yes, the address $002121* is in S-CPU address space. When the S-CPU writes to this address, the write is passed to the S-PPU, and the S-PPU sets an internal pointer to the value that the S-CPU wrote. In a sense, this pointer can be considered "memory" inside the PPU. Then when the S-CPU writes two bytes to $002122 (either through store instructions or through the DMA unit), it passes those bytes to the S-PPU. This causes the S-PPU to write those two bytes to a CGRAM entry and add 1 to the pointer, so that the next write goes to the next entry.

No, this pointer is not in work RAM. Work RAM is $7E0000-$7FFFFF, with $7E0000-$7E1FFF mirrored into $0000-$1FFF of banks $00-$3F and $80-$BF. "MMIO" (memory-mapped input and output) means that I/O ports are given addresses, which the CPU reads and writes as if they were memory.


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PostPosted: Thu Feb 09, 2017 4:52 pm 
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Thanks, this actually helps me understand things better. I think I need to do more reading regarding the SNES as a whole. So far I've only been studying the 65c816 CPU, and have a basic familiarity with other parts of the console from online resources. But you've given me the right info I need to scour more!


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PostPosted: Thu Feb 09, 2017 6:59 pm 
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Memory-mapped registers are like a "hack" that allows CPUs to talk to other pieces of hardware in the system while they think they're simply accessing memory. Some CPUs have dedicated instructions for this kind of communication (such as the Z80, which has OUT and IN instructions to send and receive data to/from other hardware), but others don't, and in those cases the systems are wired to "watch" the addresses the CPU is accessing and to redirect accesses made to "magic" locations to other parts of the system. As far as the CPU is concerned, these are just regular memory accesses, it can't know the difference, but the system is constantly watching what the CPU is doing to know what it was supposed to be interfacing with (RAM, ROM, video, audio, and so on).


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PostPosted: Fri Feb 10, 2017 3:32 am 
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- schematics
- anomie's documents
- nocash's document

The SNES CPU ("S-CPU") is the Ricoh 5A22, which uses a 65c816 core and adds some functionality like the SNES memory map, CPU waitstates (the 65c816 is halted for a certain number of master clock cycles when accessing the various memory map areas), internal registers for DMA, H/V counters etc.

65c816 addresses are 24 bits long: $00:0000..$FF:FFFF. The highest 8 bits are the bank byte (a bank is 64KB). When bank=$00..$3F or $80-$BF, all addresses of the form XX:$4000..43FF access the 5A22's registers, and addresses XX:$2100..21FF go out to address bus B (see the schematics) which is monitored by the PPU (i.e. graphics) chips, among others. So the games just write or read to "memory addresses" $XX:$21XX when they want to change the graphics.

Audio RAM, CGRAM, OAM and VRAM are separated from the CPU address lines because the A/V chips may need exclusive access to them, so you have to set the chip's read/write location and then read/write all your data to another (single) register.


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