Hmmm, yeah, I've checked some random 200ns EPROM datasheet: http://www.ti.com/lit/ds/symlink/tms27c512.pdf
and the 200ns refers to the setup time (counted from when address got stable). So the total access time might be as so:
140ns (or less) for getting address stable
200ns for the 200ns ROM/EPROM's setup time
20ns (or whatever) for the hold time needed by the target chip
plus maybe a few ns for tolerance, or in case they've specified/rounded 200ns because it was the closest commonly manufactured type.
Subtracting 3 master clocks from the total access time does make sense (in terms of explaining why nintendo specified 200ns/120ns for slow/fast ROMs). I don't know if all of that 3 master clocks are for the address, or if some are for hold time.
Are that logic analyzer traces for the SNES memory signals online somewhere, with some address lines and chip select etc?
Even if addresses seems to be stable after 1 master clock, Nintendo might have still designed the console to use 3 master clocks for getting perfectly
stable addresses (with perfect HIGH and LOW levels, and working even if there's a lot of stuff connected to cartridge slot and expansion port or other worst-case conditions).
There are some SNES CPU bus traces in this thread
, and one with a bit of annotation here
The 65816, like the original 6502, is based on a two phase clock. The clock input goes through some inverters to produce two non-overlapping clock outputs, phi1 and phi2. Basically, phi1 high is the phase when the address is being put on the address bus, and phi2 high is the phase when memory is expected to put data on the data bus, or when the CPU puts data on the bus during a write cycle. Likewise, inside the CPU some steps of each instruction cycle occur during phi1 and others occur during phi2.
In a regular 65816, the address and data busses are actually multiplexed
: during phi1 the "data" bus holds the upper 8 bits of the address (i.e. the program or data bank) and external hardware is required to latch the complete 24-bit address. In the SNES CPU the bank address latching is built in, and the external data and address busses are completely separate. In fact there are two
address busses (as you know), each having its own RD and WR signals. Basically, on the SNES CPU, the 65816 bus signals are being "translated" by on-chip hardware to something that more resembles a Z80 bus.
The 65816 core inside the SNES CPU more or less runs off of the master clock divided by 6, so phi1 and phi2 each last for 3 master clocks. However, when accessing "slow" address ranges, phi2 is stretched by 2 master clocks to a total of 5--presumably by the same on-chip hardware that's responsible for demultiplexing the bank address, differentiating A-bus and B-bus addresses and activating the appropriate RD or WR, and generating the RAMSEL and ROMSEL signals.
The important thing to note from the bus traces is that this on-chip address decoding seems to occur at the falling edge of phi1/rising edge of phi2--you can see that CPURD or CPUWR (or PARD or PAWR for B-bus addresses) aren't asserted until 3 master clocks in.