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PostPosted: Tue Feb 13, 2018 12:52 am 
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There are two PCB types for BS Memory Cartridges with mask ROM instead of flash:

Image
(click for larger image)

BSMC-CR-01 is used in the Same Game cartridge, and is a 512KiB ROM. You can read it out through $c0-c7:0000-ffff.

But if you put BSMC-BR-01, it goes poorly. It is as if A0 is not connected. So if you read $c0-c7:0000-ffff, every odd byte ends up identical to the even byte. Ex: "GNEXT DATA" reads back as "GGEETTDDTT"

In order to read this cartridge, it needs to be put in SD Gundam G Next. Only on this cartridge, it's not mapped on the bus by default. As an SA1 game, you have to set a super MMC bank to #$04 to access it. So with $2220=#$04, you can now read the BS Memory out correctly from $c0-c7:0000-ffff.

What is confusing me is ... this ROM is also 512KiB (both mirror after that), despite having four extra pins on the ROM chip. And why is there the A0 oddity on the Same Game cartridge?

I want to emulate this behavior so that if you insert BSMC-BR-01 into Same Game, it acts the same. And I still need to try reading out BSMC-CR-01 from SD Gundam G Next to see what happens.

Anyone have ideas on what might be going on here? These cartridges have an obscene amount of pins for what they are ... if someone knows the pinouts of the cartridge connector and the ROM chips, I can bring out my multimeter to trace where the mask ROM pins are going.

(Also: flash carts are BSMC-AF-01, and appear to be read out the same way as BSMC-CR-01.)


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PostPosted: Tue Feb 13, 2018 11:45 am 
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byuu wrote:
But if you put BSMC-BR-01, it goes poorly. It is as if A0 is not connected. So if you read $c0-c7:0000-ffff, every odd byte ends up identical to the even byte. Ex: "GNEXT DATA" reads back as "GGEETTDDTT"
The extra pins, and spacing between traces on the right end of the IC, implies that that's a ROM that could support a 16-bit bus. In this case, there's a pin that's pulled high or low to control whether the ROM is in 8-bit or 16-bit mode (often called "!BYTE"), and when in 8-bit mode, the D15 pin instead serves as A-1.

Quote:
What is confusing me is ... this ROM is also 512KiB (both mirror after that), despite having four extra pins on the ROM chip. And why is there the A0 oddity on the Same Game cartridge?
40 pins, 16 bit data bus, 3 pins for /CE /OE and /BYTE, usually 3 pins for power (see JEDEC 21C figure 3.5.2-4)... that's 512 KiB of data, yup.


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PostPosted: Tue Feb 20, 2018 1:27 am 
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Yes, there are 8bit/16bit databus modes. The FLASH carts support both modes. Carts with 8bit ROM chips do obviously support 8bit only. 16bit ROM chips would theoretically support both modes - but they are hardwired to 16bit mode only in the ROM cart. I've rev-engineered the pin-out a while ago; the current fullsnes.htm version still has incomplete pin-outs, so here's the latest version:
Code:
FLASH Card Slot (as found on a "BSC-1A5M-01" board)
There are two conflicting numbering schemes for the 62pin connector.
 Pin-numbering on the black plastic connector:
  Rear/Left  --> 62 ............................... 32 <-- Rear/Right
  Front/Left --> 31 ............................... 1  <-- Front/Right
 Pin-numbering on SNES cartridge PCB text layer:
  Rear/Left  --> 62 ............................... 2  <-- Rear/Right
  Front/Left --> 61 ............................... 1  <-- Front/Right
Below is using the PCB text layer's numbering scheme:
  1 GND
  2 GND
  3 D0
  4 D4 (with cap to gnd)
  5 D1 (with cap to gnd)
  6 D5
  7 D2
  8 D6
  9 D3
  10 D7
  11 A12
  12 RDY/BSY (NC) (connected in BSX-BIOS cart)
  13 A7
  14 /RD via 33 ohm R2
  15 A6
  16 /WR via 33 ohm R3      (VCC in SA1)
  17 A5
  18 /WP (VCCed) (or MCC chip)
  19 A4
  20 -     (in FLASH cart: via 47kohm R1 to VCC)
  21 A3
  22 via R4 to VCC (47kOhm) (NC in mempak)
  23 A2
  24 via R5 to GND (47kOhm) (NC in mempak)
  25 A1
  26 via R6 to GND (47kOhm) (NC in mempak)
  27 A0
  28 -     (in FLASH cart: via 47kohm R2 to VCC)
  29 A14
  30 VPP (5V)               (GND in SA1)
  31 VCC (5V or 3.3V)
  32 VCC (5V or 3.3V)
  33 via R7 to VCC (47kOhm) (NC in mempak)
  34 3V/5V (GNDed=5V)
  35 A13
  36 REFRESH    to SNES.pin.33
  37 A8
  38 A15 rom     SNES.A16 SNES.pin.41
  39 A9
  40 A16 rom     SNES.A17 SNES.pin.42
  41 A11
  42 A17 rom     SNES.A18 SNES.pin.43
  43 A10
  44 A18 rom     SNES.A19 SNES.pin.44
  45 SYSCK       SNES.pin57 (and via R1 to SNES.pin.2 EXPAND) (100 ohm)
  46 A19 rom     SNES.A20 SNES.pin.45
  47 /RESET              (or VCC in some cart/slots)
  48 A20 rom     SNES.A21 SNES.pin.46
  49 -
  50 A21 rom     SNES.A23 SNES.pin.48 (NOT SNES.A22 !!!)
  51 /CS (from MAD-1A.pin1, SA1.pin81, MCC-BSC.pin23)
  52 /BYTE (GNDed) (VCC in SA1 carts)
  53 D12 (NC)
  54 D11 (NC)
  55 D13 (NC)
  56 D10 (NC)     ... pins here are D8-D15 (on PCBs with 16bit databus)
  57 D14 (NC)
  58 D9  (NC)
  59 D15 (NC)
  60 D8  (NC)
  61 GND
  62 GND

pitch: 38.1mm per 30 pins === 1.27mm per pin (similar to 50pin Compact Flash)
There are some connection variants: The Itoi cartridge with SA-1 is using 16bit databus (with extra data lines on pin53-60), pin12 seems to be connected to something, some of the pull-up/pull-downs and VCC/GND pins on pin 14-34 and 52 may be wired differently.

SNES Cartridge Slot Usage for Satellaview BIOS and Datapack carts
REFRESH (SNES.pin33) is forwarded to FLASH cart slot (for unknown reason, maybe it was intended for unreleased DRAM cartridges).
SYSCK (SNES.pin57) is forwarded to FLASH cart slot (for unknown reason), and is also forwarded (via 100 ohms) to EXPAND (SNES.pin2) (and from there forwarded to the BSX Receiver Unit on SNES Expansion port).


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PostPosted: Tue Feb 20, 2018 1:08 pm 
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lidnariq's post seemed reasonable enough, but ...

Quote:
they are hardwired to 16bit mode only in the ROM cart


How in the world?? The SNES is an 8-bit data bus. Why would they wire a ROM to 16-bit data mode? How would that even work??


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PostPosted: Tue Feb 20, 2018 2:57 pm 
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Joined: Fri Feb 24, 2012 12:09 pm
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The datapak ROM connects to the SA1 chip, not to the SNES cpu.
16bit databus isn't so uncommon in SNES carts - it's used by SA1 games, and at least by some games with data-decompression chips. The only uncommon thing is that the 16bit datapaks are removeable - allowing to connect them to other carts that can't read them in lack of 16bit bus.


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PostPosted: Tue Feb 20, 2018 10:21 pm 
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Yes, but what can the SA1 CPU do with that?

The SA1 is yet another 65816 that can only read 8-bits per clock cycle.


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PostPosted: Tue Feb 20, 2018 10:36 pm 
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I was under the impression that it had a memory controller to feed the CPU one byte at a time, which would explain how it manages 10.74 MHz on affordable ROM but sees wait states whenever it hits a branch or data access.


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