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PostPosted: Thu Apr 26, 2018 4:02 pm 
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koitsu wrote:
Respectfully, this description is no better than any of the existing documentation. :\ Which is it?

a) B0->$21xx B0->$21xx (e.g. byte 0 of source written to $21xx, followed by byte 0 of source written to $21xx)
b) B0->$21xx B1->$21xx (e.g. byte 0 of source written to $21xx, followed by byte 1 of source written to $21xx)

The latter.

Quote:
Two writes to a single MMIO register still technically is "transferring" two bytes of data.

Sure, but given that there is literally no register that requires/expects you to always write the same value to it twice at a time (versus several registers that are 16-bit write-twice), I think it's pretty obvious that "2 bytes" in Nintendo's docs means the same thing for that mode that it does for every other multiple-byte mode, w/r/t reading data from the source address.

The misinformation about %010 being the same as %000 probably just stemmed from people only testing it with regular DMA, where it is functionally identical since you're measuring the source data size in bytes instead of scanlines.


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PostPosted: Thu Apr 26, 2018 9:26 pm 
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Revenant wrote:
The latter.

Awesome -- thank you!

Revenant wrote:
Sure, but given that there is literally no register that requires/expects you to always write the same value to it twice at a time (versus several registers that are 16-bit write-twice), I think it's pretty obvious that "2 bytes" in Nintendo's docs means the same thing for that mode that it does for every other multiple-byte mode, w/r/t reading data from the source address.

The misinformation about %010 being the same as %000 probably just stemmed from people only testing it with regular DMA, where it is functionally identical since you're measuring the source data size in bytes instead of scanlines.

Could I ask for you to expand on this, particularly the 2nd paragraph? I don't see how in general DMA mode %010 is identical to %000. Sorry if I sound like a broken record, but B0->$21xx and B0->$21xx B1->$21xx are most certainly not the same.


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PostPosted: Fri Apr 27, 2018 7:59 am 
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With HDMA, it matters because it changes the number of bytes that are transferred per scanline (from 1 byte to 2). With regular DMA, $43x5/43x6 measure the total transfer size in bytes regardless of which transfer mode you use, so those two modes end up doing basically the same thing. That's why I think some early documentation had that mistake, just because the difference isn't apparent unless you're using one of them with HDMA instead of regular DMA.


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PostPosted: Fri Apr 27, 2018 4:48 pm 
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I'm still having stack issues. Within my NMI, the RTI is not returning back to bank $80 which I set it to. It keeps going to bank $A5? :-/

Code:
008200 jml $808204   [808204] A:0081 X:8000 Y:2000 S:01fb D:0000 DB:00 NvMxdIzC V:257 H: 10 F: 1
808204 rep #$30               A:0081 X:8000 Y:2000 S:01fb D:0000 DB:00 NvMxdIzC V:257 H: 18 F: 1
808206 lda #$8200             A:0081 X:8000 Y:2000 S:01fb D:0000 DB:00 NvmxdIzC V:257 H: 24 F: 1
808209 pha                    A:8200 X:8000 Y:2000 S:01fb D:0000 DB:00 NvmxdIzC V:257 H: 30 F: 1
80820a phx                    A:8200 X:8000 Y:2000 S:01f9 D:0000 DB:00 NvmxdIzC V:257 H: 37 F: 1
80820b phy                    A:8200 X:8000 Y:2000 S:01f7 D:0000 DB:00 NvmxdIzC V:257 H: 45 F: 1
80820c phd                    A:8200 X:8000 Y:2000 S:01f5 D:0000 DB:00 NvmxdIzC V:257 H: 52 F: 1
80820d phb                    A:8200 X:8000 Y:2000 S:01f3 D:0000 DB:00 NvmxdIzC V:257 H: 60 F: 1
80820e rep #$10               A:8200 X:8000 Y:2000 S:01f2 D:0000 DB:00 NvmxdIzC V:257 H: 65 F: 1
808210 sep #$20               A:8200 X:8000 Y:2000 S:01f2 D:0000 DB:00 NvmxdIzC V:257 H: 71 F: 1
808212 lda #$00               A:8200 X:8000 Y:2000 S:01f2 D:0000 DB:00 NvMxdIzC V:257 H: 76 F: 1
808214 sta $2102     [002102] A:8200 X:8000 Y:2000 S:01f2 D:0000 DB:00 nvMxdIZC V:257 H: 80 F: 1
808217 sta $2103     [002103] A:8200 X:8000 Y:2000 S:01f2 D:0000 DB:00 nvMxdIZC V:257 H: 88 F: 1
80821a ldy #$0400             A:8200 X:8000 Y:2000 S:01f2 D:0000 DB:00 nvMxdIZC V:257 H: 95 F: 1
80821d sty $4300     [004300] A:8200 X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:101 F: 1
808220 stz $4302     [004302] A:8200 X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:110 F: 1
808223 lda #$02               A:8200 X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:118 F: 1
808225 sta $4303     [004303] A:8202 X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:122 F: 1
808228 lda #$7e               A:8202 X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:129 F: 1
80822a sta $4304     [004304] A:827e X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:133 F: 1
80822d ldy #$0100             A:827e X:8000 Y:0400 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:151 F: 1
808230 sty $4305     [004305] A:827e X:8000 Y:0100 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:157 F: 1
808233 lda #$01               A:827e X:8000 Y:0100 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:166 F: 1
808235 sta $420b     [00420b] A:8201 X:8000 Y:0100 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:170 F: 1
808238 sep #$10               A:8201 X:8000 Y:0100 S:01f2 D:0000 DB:00 nvMxdIzC V:257 H:177 F: 1
80823a lda #$80               A:8201 X:0000 Y:0000 S:01f2 D:0000 DB:00 nvMXdIzC V:259 H: 29 F: 1
80823c sta $2102     [002102] A:8280 X:0000 Y:00fc S:01f2 D:0000 DB:00 NvMXdIzC V:259 H: 33 F: 1
80823f lda #$00               A:8280 X:0000 Y:00fc S:01f2 D:0000 DB:00 NvMXdIzC V:259 H: 40 F: 1
808241 sta $2103     [002103] A:8200 X:0000 Y:00fc S:01f2 D:0000 DB:00 nvMXdIZC V:259 H: 44 F: 1
808244 ldy #$00               A:8200 X:0000 Y:00fc S:01f2 D:0000 DB:00 nvMXdIZC V:259 H: 52 F: 1
808246 ldx #$00               A:8200 X:0000 Y:0000 S:01f2 D:0000 DB:00 nvMXdIZC V:259 H: 56 F: 1
808248 lda $81fc,x   [0081fc] A:8200 X:0000 Y:0000 S:01f2 D:0000 DB:00 nvMXdIZC V:259 H: 60 F: 1
80824b sta $2104     [002104] A:8200 X:0000 Y:0000 S:01f2 D:0000 DB:00 nvMXdIZC V:259 H: 68 F: 1
80824e inx                    A:8200 X:0000 Y:0000 S:01f2 D:0000 DB:00 nvMXdIZC V:259 H: 75 F: 1
80824f lda $81fc,x   [0081fd] A:8200 X:0001 Y:0000 S:01f2 D:0000 DB:00 nvMXdIzC V:259 H: 79 F: 1
808252 sta $2104     [002104] A:82e0 X:0001 Y:0000 S:01f2 D:0000 DB:00 NvMXdIzC V:259 H: 87 F: 1
808255 inx                    A:82e0 X:0001 Y:0000 S:01f2 D:0000 DB:00 NvMXdIzC V:259 H: 94 F: 1
808256 cpx #$04               A:82e0 X:0002 Y:00fc S:01f2 D:0000 DB:00 nvMXdIzC V:259 H: 98 F: 1
808258 bne $825c     [80825c] A:82e0 X:0002 Y:00fc S:01f2 D:0000 DB:00 NvMXdIzc V:259 H:102 F: 1
80825c iny                    A:82e0 X:0002 Y:00fc S:01f2 D:0000 DB:00 NvMXdIzc V:259 H:107 F: 1
80825d iny                    A:82e0 X:0002 Y:00fd S:01f2 D:0000 DB:00 NvMXdIzc V:259 H:111 F: 1
80825e cpy #$fe               A:82e0 X:0002 Y:00fe S:01f2 D:0000 DB:00 NvMXdIzc V:259 H:114 F: 1
808260 bne $8248     [808248] A:82e0 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:118 F: 1
808262 lda #$00               A:82e0 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:122 F: 1
808264 sta $2102     [002102] A:8200 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:126 F: 1
808267 pha                    A:8200 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:134 F: 1
808268 lda #$01               A:8200 X:0002 Y:00fe S:01f1 D:0000 DB:00 nvMXdIZC V:259 H:149 F: 1
80826a sta $2103     [002103] A:8201 X:0002 Y:00fe S:01f1 D:0000 DB:00 nvMXdIzC V:259 H:153 F: 1
80826d pla                    A:8201 X:0002 Y:00fe S:01f1 D:0000 DB:00 nvMXdIzC V:259 H:161 F: 1
80826e sta $2104     [002104] A:8200 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:168 F: 1
808271 sta $2104     [002104] A:8200 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:175 F: 1
808271 sta $2104     [002104] A:8200 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:175 F: 1
808274 plb                    A:8200 X:0002 Y:00fe S:01f2 D:0000 DB:00 nvMXdIZC V:259 H:183 F: 1
808275 pld                    A:8200 X:0002 Y:00fe S:01f3 D:0000 DB:00 nvMXdIZC V:259 H:190 F: 1
808276 ply                    A:8200 X:0002 Y:00fe S:01f5 D:0000 DB:00 nvMXdIZC V:259 H:199 F: 1
808277 plx                    A:8200 X:0002 Y:0000 S:01f6 D:0000 DB:00 nvMXdIZC V:259 H:206 F: 1
808278 pla                    A:8200 X:0020 Y:0000 S:01f7 D:0000 DB:00 nvMXdIzC V:259 H:213 F: 1
808279 rti                    A:8200 X:0020 Y:0000 S:01f8 D:0000 DB:00 nvMXdIZC V:259 H:220 F: 1

here is the issue, it's going to bank $A5???
a58200 inx                    A:8200 X:0020 Y:0000 S:01fc D:0000 DB:00 Nvmxdizc V:259 H:233 F: 1


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PostPosted: Fri Apr 27, 2018 4:51 pm 
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infidelity wrote:
008200 jml $808204 [808204] A:0081 X:8000 Y:2000 S:01fb D:0000 DB:00 NvMxdIzC V:257 H: 10 F: 1
[...]
808279 rti A:8200 X:0020 Y:0000 S:01f8 D:0000 DB:00 nvMXdIZC V:259 H:220 F: 1
Your stack use is unbalanced. Make sure you pull and push the same number of bytes in every possible execution path.


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PostPosted: Fri Apr 27, 2018 5:26 pm 
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Thank You!

I used the bsnes debugger and stepped through my NMI, turns out it had to deal with how I had my REP's & SEP's placed near the beginning and end of my NMI. I made it so when the NMI starts (before pushing everything) that I set A,X,Y to 8-bits. Then, at the end of the NMI (before pulling everything) I make sure to set A,X,Y to 8-bits again, then when I watch the stack address during pulling, it matched the address it was before the pushing, resulting in going back to my reset vector infinite loop. :-)


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PostPosted: Fri Apr 27, 2018 6:09 pm 
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You should instead set them all to 16-bit before pushing/popping to make sure that the upper bytes of A/X/Y aren't destroyed whenever an interrupt occurs.

e: especially if X/Y were already 16-bit when the interrupt occurs, because setting the index registers to 8-bit will destroy the upper bytes automatically.


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PostPosted: Fri Apr 27, 2018 6:58 pm 
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I suggest getting familiar with php and plp. Revenant's advice is highly applicable alongside that.


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PostPosted: Sat Apr 28, 2018 3:45 am 
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Ooooh, ok. Thank you both for that info! I'll add that today and step through to watch the stack. :-)


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PostPosted: Tue May 01, 2018 4:22 am 
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I've got another question regarding loading long. Are you able to load a ROM value long, with X and Y? Opcodes I heavily used were B9####(LDA'Y) & BD####(LDA'X)

Can I do this with using long, reading values from other banks that other banks, that my loading code is currently not in?


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PostPosted: Tue May 01, 2018 7:26 am 
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http://www.6502.org/tutorials/65c816opcodes.html#5.17
https://wiki.nesdev.com/w/images/7/76/Programmanual.pdf pg52 etc.


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PostPosted: Tue May 01, 2018 7:48 am 
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I also recommend http://oxyron.de/html/opcodes816.html as a quick cheat sheet, especially if you're already familiar with the original 6502 instructions. It lists all opcodes in a table along with their addressing mode and cycle count, plus notes about which flags they affect, etc.


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PostPosted: Tue May 01, 2018 12:57 pm 
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As I said in a previous post on the previous page:

Quote:
If you don't have a 65816 instruction manual by now, then get it. ...

Said manual is easy to understand and goes over all the addressing modes. There is also an opcode breakdown in Chapter 13 that makes it easier to remember what opcode supports what addressing mode.

In short: yes, there are 24-bit long indexed addressing modes, and yes you can use them to access anything in the entire 24-bit address space of the 65816. But I'm not going to go into the rest because I'm going to make you get the manual and read it. :-) Make sure you understand the B register (bank; sometimes called DB (data bank)) as well (relates to 16-bit addressing). Don't confuse this with the upper vs. lower bytes of the 16-bit accumulator (which are often called "A" and "B", hence xba opcode).

Next, be aware that different assemblers use different syntax for long addressing. Refer to your assembler documentation for how. And most use [] (brackets, not parenthesis!) for indirect long addressing, but again, it depends on the assembler.

Finally, if you're using WLA DX, you may need to get familiar with using the .b and .w and .l suffixes on opcodes, ex. lda.b vs. lda.w vs. lda.l, to tell the assembler what addressing mode / "operand length" you want to use (8-bit vs. 16-bit vs. 24-bit). You can also put those suffixes on the end of the operand, but that tends to look incredibly gross/ugly. There's docs on that here and here (look up .8bit, .16bit, .24bit in Section 2, and ESPECIALLY see Section 14.5). Sometimes it can figure it out on its own, other times it cannot -- and when it can't, or picks the wrong one, you'll need assembly listings to figure it out (or step through the code in a debugger and see that it's using the wrong opcode/addressing mode).


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