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 Post subject: Megaman X3 Project Zero
PostPosted: Mon May 28, 2018 11:30 am 
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Hi there. I assume it is not possible to use x2 pcb for donor board as it should only support up to 2mb? Can anyone help with finding the datasheet for the lh5379na eeprom found on an x3 pcb? Or does anyone know what chips could be used to do this one?


Last edited by rocklite on Mon May 28, 2018 12:41 pm, edited 1 time in total.

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PostPosted: Mon May 28, 2018 11:48 am 
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rocklite wrote:
lh5379na eeprom
That's a Mask ROM, not EEP.

The CX4 pinout is known. I believe the Mask ROMs are standard JEDEC order. Other than having one vs two ROMs, the only difference between the 1DC0N and 2DC0N boards is that the software run on the SNES writes one bit or another to the CX4 which controls whether the pin A20 contains a real signal (and /ROM1 is used exclusively) or whether A20 is ignored and /ROM1 and /ROM2 select between the first and 2nd megabyte.


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PostPosted: Mon May 28, 2018 2:50 pm 
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The surface mount MaskROMs on Cx4 and GSU boards have the same pinout as the through-hole MaskROMs on most carts, for both the 32 and 36 pin packages. For some reason, Sharp used the LH538 part number for some SNES MaskROMs as well as Game Boy ones, but the pinouts are NOT the same between them.

Here's the pinout for the Game Boy one for comparison:
Image


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PostPosted: Mon May 28, 2018 10:11 pm 
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Potentially it could work on x2 if you could patch the roms to use both banks i presume. I managed to get tsop40 36pin chips to work on x2 board by grounding the leftover pins on the chip.
Ine curiousity though is that I found an image of Retrostage's sfx tsop converter with some info about using x2 in an x3 board. it states that you need a software patch to run x2 on an x3 board. Retrostages adapter has the same pinout as standard 32pin mask like x2 pcb. Perhaps this is evidence that the 40pin mask chip in x3 does at some point share the same pinout? And if not, perhaps i could isolate which pins go to the cx4 and wire it up that way? Either way would it be ok to leave the leftover mask pins on the board clean without wires?


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PostPosted: Mon May 28, 2018 11:38 pm 
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rocklite wrote:
it states that you need a software patch to run x2 on an x3 board.
More information here
Quote:
Perhaps this is evidence that the 40pin mask chip in x3 does at some point share the same pinout?
I honestly don't know.

I can compare pictures of the 1DC0N and 2DC0N boards that are on snescentral.com, but it's not obvious from those pictures what the pinout of the LH5379 ROM is. Most of the visible traces go to vias where I can't see what happens afterwards. The few pins that I can make out are:
Code:
rom cx4 signal
35  27  /CE
34  28  A19
33  35  A14
32  36  A13
29  38  A11
27  39  A10
18  59  D1
17  60  D0


Quote:
And if not, perhaps i could isolate which pins go to the cx4 and wire it up that way?
Yes, but hopefully that's not necessary... You should just start with getting a pinout for the LH5379 and see if things work out.

Quote:
Either way would it be ok to leave the leftover mask pins on the board clean without wires?
Yes, on a 2DC0N board you only need to put something on the lands for U2 if the CX4 is configured to look for data in it.


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PostPosted: Tue May 29, 2018 7:08 am 
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qwertymodo wrote:
Here's the pinout for the Game Boy one for comparison:
picture


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PostPosted: Tue May 29, 2018 2:20 pm 
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Image

back of rmx3 pcb


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PostPosted: Tue May 29, 2018 2:51 pm 
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If you have the physical PCB, it will honestly be faster for you to sit down with a multimeter and use the continuity meter to figure out what pin is connected to what than for me to stitch the pictures together and guess where traces are under the ICs.

edit: the text in the linked image below is from fullsnes § SNES pinouts ROM chips


Last edited by lidnariq on Thu May 31, 2018 11:56 am, edited 1 time in total.

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PostPosted: Tue May 29, 2018 10:23 pm 
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Id bet its this standard 40 pin one. First time seeing one personally.
[That's a bit big for a "tiny" pic --MOD]


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PostPosted: Mon Jun 04, 2018 10:52 am 
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Wired in a tsop to dip36 chip and found game hangs / stops after capcom logo... left the last 4 traces (vcc and gnd) on the board be instead of connecting to chip though.


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PostPosted: Mon Jun 04, 2018 11:07 am 
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Did you do any rework? The 2DC0N board doesn't connect CX4 A20 to anything; if you're replacing two ROMs containing MMX2 with one ROM containing MMX3 you'll need to add that signal.


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PostPosted: Mon Jun 04, 2018 7:32 pm 
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I am trying to put the awesome Rockman X3 hack known as " Project Zero " on a 1DC0N board.
I am not working with x2 or trying to put x3 on a 2dc0n board at all. That was another project and I know how to do that. I am trying to replace one 1.5mb 40pin mask rom with one 4mb 36pin 29f033c chip.


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PostPosted: Mon Jun 04, 2018 8:48 pm 
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Oh. No.

The CX4 can only address 2 MiB of data ... you'll note that Project Zero has 4.

It turns out you can't do this in one ROM; you have to use two. One is readable by the CX4, the other is only readable by the SNES.

here's a previous thread about this.


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PostPosted: Fri Jun 15, 2018 10:36 am 
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rocklite wrote:
Id bet its this standard 40 pin one. First time seeing one personally.
[That's a bit big for a "tiny" pic --MOD]


This pinout is almost correct, but /CS and /RD are swapped (a lot of pinouts you find online get them backwards because Nintendo likes to play fast and loose with those two signals on their MaskROMs). The pinout for the MMX2 ROMs is the same, just remove pins 1-4 and 37-40.

Edit: Here are the correct pinouts https://www.caitsith2.com/snes/flashcar ... s.html#rom


Last edited by qwertymodo on Mon Jun 18, 2018 4:41 pm, edited 1 time in total.

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PostPosted: Mon Jun 18, 2018 2:52 pm 
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rocklite wrote:
I am trying to put the awesome Rockman X3 hack known as " Project Zero " on a 1DC0N board.
I am not working with x2 or trying to put x3 on a 2dc0n board at all. That was another project and I know how to do that. I am trying to replace one 1.5mb 40pin mask rom with one 4mb 36pin 29f033c chip.


I've done it, but it's not too straightforward.
The main issue is that the CX4 doesn't know where to map ROM data past 2MB, causing it not to enable the ROMs /OE line.
I'm not entirely sure of the process but I have some notes:

- hack is based on MMX3 but I used 2-ROMs on a MMX2 board I changed that $7f52 register to be set to 0 instead of 1
- the data lines are passed from edge connector through CX4 to ROM, but CX4 tristates data lines (luckily not address lines!) when we're reading past 16mbit in ROM, so we have to run the data lines from ROM2 directly to the edge connector
- for simplicity, both ROM1 and ROM2 can have their /CE tied to GND and we'll do all switching on the /OE lines
- ROM1 will need the A20 line from the CX4 and the CX4 /ROMOE line can be used for the ROM1 /OE signal
- ROM2 is to be enabled while /ROMSEL is low and we're reading past the 16-mbit address on the bus. This is LoROM so that would be edge A22.
- instead of having the data pass through cx4, I placed the upper 16mbit in parallel with the cx4 directly on the edge connector. Then
the enable clause for the 2nd EEPROM is simply ~A22 || /ROMSEL.
So to modify a MMX2 board you:
- patch ROM file to set $7f52 to 1 instead of 0
- route ROM1 /CE to ground, /OE to cx4 pin 52 (/ROE)
- cut ROM2 data line traces to cx4 (behind the via's so ROM1 data
lines remain connected)
- route ROM2 data lines to edge connector using the pads next to C11-C17 marking
- route ROM2 /CE to ground, /OE to some logic formula (I used a 74139)
- get A20 from CX4 (no /CE trickery possible this time)


Image
Image


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