magno wrote: Or did you implement full SNES in an FPGA? That would be great then!
Great!! It would be nice there were some open-sorce projects for SNES FPGA implementation. It could be use for homebrew, getting the most of SNES system, adding features...
magno wrote:Of course SRAM is present, 8 Mbyte split by 6 Mbyte for ROM and 2 Mbyte (used 8Kbyte) for backup SRAM. When I'm home, I'll post its source.
Maybe there is something I missed or you don't understand what I mean
S-DD1 chip is the address decoder for ROM and backup SRAM in the real cartridge, and so it should be in your FPGA design (there can't be 2 address decoders driving the same signals), so anytime CPU accesses ROM or backup SRAM, S-DD1 decodes the address and then reads ROM or backup SRAM.
In your SDD1 implementation, there isn't any output signal for enabling ROM access, even if you implement ROM in SRAM chips, so if SNES reads from $C0:8001... how do you enable ROM to read from it? There isn't such signal in your design.
As for backup SRAM, the same happens... But in this case, if CPU reads from backup SRAM to get some data needed by audio engine, your S-DD1 implementation won't decode the backup SRAM address, so the CPU won't get the proper data. Then, the audio engine will stall, and Star Ocean will freeze. In your videos, Star Ocean runs fine, so there is something weird on that...