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PostPosted: Sun Aug 05, 2018 1:14 pm 
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Hello.

Here is a diagram of the memory map of the 65816:

Image



Well, i have some questions about this table (or maybe some notions that i need to verify):

1) The total amount of directionable memory comes determined by data bus bandwidth (24 bits --> 16 bits of data adressing, and 8 bits of data banking)... Am I right?.

2) According to this, 16 bits means in hexadecima that you have 16 positions of memory in this way (0, 1, 2, 3 , 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)... Is it correct?.

3) The diagram shows an horizontal column from $FF to $00 (the orden of it is caused by little endian storing format?), but there are some blocks without reference, but still some of it must be missing.

We have vertically from $0000 to $FFFF, and the horizontally $FF to $00, but there have blocks to be missing, What is happening?.

4) In all of that diagram is supossed that there are 16MB, and some of these are reserved fro WRAM, VRAM, ARAM, some SRAM for cartridges, and may be another not mentioned ones... which could be the total amount of directionable memory in ROM with a custom decoder?.


Thank you.


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PostPosted: Sun Aug 05, 2018 1:31 pm 
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Some parts of the 65816's 16 MiB address space are indeed unassigned.

VRAM, OAM (sprite display list), CGRAM (palette), and ARAM are separate address spaces in memory that is physically separate from the 65816. They don't overlap unused parts of the 65816's 16 MiB address space. They may be read or written only through an interface provided by another IC on the Control Deck's PCB.


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PostPosted: Sun Aug 05, 2018 1:40 pm 
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Señor Ventura wrote:
Here is a diagram of the memory map of the 65816

No, that's the memory map of the SNES 5A22, which does contain a 65816 core. (Also, some game cartridges contain a SA1 which also contains a 65816 core and which has an entirely different memory map.)

Señor Ventura wrote:
1) The total amount of [addressable] memory is determined by the [address] bus [width] (24 bits --> 8 [bank] bits and 16 [offset] bits)

Fixed that for you.

2^24 bytes would be the total amount of addressable memory, but in the SNES several areas of this memory map are already reserved.

Señor Ventura wrote:
2) According to this, 16 bits means in hexadecima that you have 16 positions of memory in this way (0, 1, 2, 3 , 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)

16 bits means 2^16 = 65536 addresses.

Use the memory map in the link above. Note that cartridges can map their components into the map however they want, as long as the game code knows about the exact location. So different games may map SRAM to different addresses. Also note that cartridges can do bank switching if they have the necessary hardware.


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PostPosted: Sun Aug 05, 2018 1:50 pm 
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Quote:
16 bits means


a "16 bit processor", means that it has a 16 bit word size.

That means it can add, subtract, bit shift, etc across 16 bits. It can load or store 16 bits in one move.

_________________
nesdoug.com -- blog/tutorial on programming for the NES


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PostPosted: Sun Aug 05, 2018 2:00 pm 
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Quote:
VRAM, OAM (sprite display list), CGRAM (palette), and ARAM are separate address spaces in memory that is physically separate from the 65816


Just to add a little. VRAM is a separate 64k RAM chip (confusingly, actually 32k of 16-bit words), that is accessed through hardware registers.

The OAM is another separate RAM chip of 544 bytes, accessed through hardware registers.

The CGRAM is another 512 byte RAM chip, accessed through hardware registers.

The Audio chip (Sony SPC700) has it's own RAM chip, that is accessed through some hardware registers, and it runs it's own program, which has to be loaded at startup.

_________________
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PostPosted: Sun Aug 05, 2018 5:54 pm 
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Yes, thank you to all... the 65816 doesn't access to the vram, so its memory map doesn't includes that 64KB, it was obvious, i was hurry to finish the post.

And the ARAM is managed by the spc700, so, the same here.

tepples wrote:
Some parts of the 65816's 16 MiB address space are indeed unassigned.


So, i noticed well, there are memory position that aren't included in the diagram, right?, so, What happens if you try to access to one of that adress spaces?.

creaothceann wrote:
Fixed that for you.

2^24 bytes would be the total amount of addressable memory, but in the SNES several areas of this memory map are already reserved.


Yes, that is the point 2^24 are 16MB addressable, but you can count only 95 megabits reserved for ROMs.

The question is if it could be achieved near the whole 16MB with a custom decoder.


I put this here for later:

=============================================================================
Anomie's SNES Memory Mapping Doc
$Revision: 1160 $
$Date: 2008-12-21 12:40:39 -0500 (Sun, 21 Dec 2008) $
<anomie@users.sourceforge.net>
=============================================================================

This is a document intended to describe the SNES memory map. It will NOT
include information on the MAD-1 or any other address decoder.

HARDWARE
========

The SNES has one 8-bit data bus, two address busses typically known as
"Address Bus A" and "Address Bus B".

Data Bus
--------

The data bus is 8 bits. If nothing sets a value on the data bus for any
particular read request, the last value placed on the bus is read instead
(this is known as "Open Bus").

LINE | CART | EXPAND
-----+------+--------
D0 | 19 | 11
D1 | 20 | 12
D2 | 21 | 13
D3 | 22 | 14
D4 | 50 | 15
D5 | 51 | 16
D6 | 52 | 17
D7 | 53 | 18

Address Bus A
-------------

This address bus is 24 bits, along with read and write lines (/RD and /WR)
and 2 auxiliary lines (/CART and /WRAM). WRAM is connected to this bus, as
well as the cart connector.

LINE | CART LINE | CART
-----+------ -------+------
A0 | 17 A14 | 39
A1 | 16 A15 | 40
A2 | 15 A16 | 41
A3 | 14 A17 | 42
A4 | 13 A18 | 43
A5 | 12 A19 | 44
A6 | 11 A20 | 45
A7 | 10 A21 | 46
A8 | 9 A22 | 47
A9 | 8 A23 | 48
A10 | 7 /RD | 23
A11 | 6 /WR | 54
A12 | 37 /CART | 49
A13 | 38 /WRAM | 32

Address Bus B
-------------

This address bus is 8 bits, along with read and write lines (/RD and /WR).
d /WRAM). WRAM, PPU1, PPU2, and APU are connected to this bus, as well as
the cart and expansion ports.

LINE | CART | EXPAND
-----+------+--------
PA0 | 28 | 1
PA1 | 59 | 2
PA2 | 29 | 3
PA3 | 60 | 4
PA4 | 30 | 5
PA5 | 61 | 6
PA6 | 3 | 7
PA7 | 34 | 8
/PARD| 4 | 10
/PAWR| 35 | 9


MEMORY MAP
==========

As far as the SNES is concerned, this is the memory map. "LoROM", "HiROM",
and anything else is just the cart responding differently to the addresses
placed on Address Bus A.

WRAM responds to Address Bus A whenever /WRAM is active, and to registers
$2180-$2183 on Address Bus B. APU responds to $40-$7F on Address Bus B. PPU1
and PPU2 respond to $2100-$213F on Address Bus B. The cart is expected to
respond when /CART is active, but it can respond to any address on either bus
that is not otherwise mapped. Similarly, the device plugged into the expansion
port may respond to any unmapped register on Address Bus B.

The 'Speed' column indicates the memory access speed for that area of memory.
The SNES master clock runs at about 21MHz (probably as close to 1.89e9/88 Hz as
possible). Internal operation CPU cycles always take 6 master cycles. Fast
memory access cycles also take 6 master cycles, Slow memory access cycles take
8 master cycles, and XSlow memory access cycles take 12 master cycles.


Banks | Addresses | Speed | Mapping
---------+-------------+-------+---------
$00-$3F | $0000-$1FFF | Slow | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
| $2000-$20FF | Fast | Address Bus A
| $2100-$21FF | Fast | Address Bus B
| $2200-$3FFF | Fast | Address Bus A
| $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
| $4200-$43FF | Fast | Internal CPU registers (see Note 1 below)
| $4400-$5FFF | Fast | Address Bus A
| $6000-$7FFF | Slow | Address Bus A
| $8000-$FFFF | Slow | Address Bus A + /CART
---------+-------------+-------+---------
$40-$7D | $0000-$FFFF | Slow | Address Bus A + /CART
---------+-------------+-------+---------
$7E-$7F | $0000-$FFFF | Slow | Address Bus A + /WRAM
---------+-------------+-------+---------
$80-$BF | $0000-$1FFF | Slow | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
| $2000-$20FF | Fast | Address Bus A
| $2100-$21FF | Fast | Address Bus B
| $2200-$3FFF | Fast | Address Bus A
| $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
| $4200-$43FF | Fast | Internal CPU registers (see Note 1 below)
| $4400-$5FFF | Fast | Address Bus A
| $6000-$7FFF | Slow | Address Bus A
| $8000-$FFFF | Note2 | Address Bus A + /CART
---------+-------------+-------+---------
$C0-$FF | $0000-$FFFF | Note2 | Address Bus A + /CART

Note 1: The address for internal CPU registers may go out Address Bus A,
however the CPU ignores the data bus. It is unknown whether the data bus
is ignored for the whole memory region, or just for those addresses which
are actually registers. It is also unknown whether CPU writes show up on
the data bus or not. Current theory is that addresses and writes will show
up, but reads may or may not, and the data bus is only ignored for those
bits of those registers actually mapped (e.g., data bus is ignored for only
bit 7 of $4211).

Note 2: If bit 0 of CPU register $420d is set, the speed is Fast, otherwise
it is Slow.



=============================================================================
HISTORY:

Version 1.1: Jun 18, 2003
* Tested the memory access speed of all 256-byte memory blocks, and filled in
the table with the findings.

Version 1.0:
* Initial version.

creaothceann wrote:
16 bits means 2^16 = 65536 addresses.


Yes, you have 16 positions in hexadecimal in horizontal x vertical.

dougeff wrote:
a "16 bit processor", means that it has a 16 bit word size.


Yes, high Byte and low Byte, but the diagram has 16 adress position in hexadecima in horizontal and vertical. i meant that the memory mapping is about the processor, but the amount addressable is about the adress bus (16 bits + 8 bits).

dougeff wrote:
Just to add a little. VRAM is a separate 64k RAM chip (confusingly, actually 32k of 16-bit words), that is accessed through hardware registers.

The OAM is another separate RAM chip of 544 bytes, accessed through hardware registers.

The CGRAM is another 512 byte RAM chip, accessed through hardware registers.

The Audio chip (Sony SPC700) has it's own RAM chip, that is accessed through some hardware registers, and it runs it's own program, which has to be loaded at startup.


Yes, thank you, i didn't think about it so well xD


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PostPosted: Sun Aug 05, 2018 6:29 pm 
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Señor Ventura wrote:
So, what happens if you try to access to one of those address spaces?

Then you need to look at what happens when the CPU does a read access.

The 65* chip family operates with a 2-phase clock signal. In the first phase (PHI1) of each CPU clock cycle, the CPU sets the "RWB" (read/write bit) line, and puts a value on the data bus if it's writing a value. In the second phase (PHI2) of each CPU clock cycle, the hardware connected to the CPU reacts to the values on these lines. The WRAM for example puts a value on the data bus if it was a read access, or stores the value if it was a write access; other hardware, for example the PPU, may even react to read accesses by changing some internal register.

If you execute a read instruction (e.g. LDA $3412), the CPU reads the opcode ($AD = LDA), then the first byte of the operand ($12) and then the second byte of the operand ($34). So after loading the complete instruction, the the CPU's MDR contains the value $34. Assuming there's no hardware mapped to address $3412, the MDR simply remains unchanged. At the end, the value in the CPU's accumulator will be $34 if it's in 8-bit transfer mode, or $3434 if it's in 16-bit transfer mode.


Señor Ventura wrote:
Yes, that is the point 2^24 are 16MB addressable, but you can count only 95 megabits reserved for ROMs.

The question is if it could be achieved near the whole 16MB with a custom decoder.

No, because the hardware that already exists in the SNES can't just be deactivated.


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PostPosted: Sun Aug 05, 2018 7:53 pm 
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You could get to just under 15 MB if you put ROM literally everywhere that isn't already taken.

viewtopic.php?f=12&t=4380&p=105068#p105068

The cartridge design would be no cakewalk, but it's possible. Any more than that requires a mapper chip.


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PostPosted: Sun Aug 05, 2018 8:30 pm 
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93143 wrote:
The cartridge design [of the 119Mibit cart] would be no cakewalk, but it's possible.
Horrible tangent: It's trivial.

Because of how the existing map is, you can use /ROMSEL to simplify the logic. Just A0-A14, A22, and /ROMSEL is sufficient. It'd both fit in an inexpensive 16V8 and be fast enough.


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PostPosted: Mon Aug 06, 2018 1:08 pm 
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...but you told me...

Oh well. That's what I get for trying to infer something beyond my expertise and stating it as a fact...


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PostPosted: Mon Aug 06, 2018 1:18 pm 
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There's also a huge difference between what makes sense for hobbyists now and what made sense for N at the time. Given that the largest game they published for the SNES was 6 MiB (right?), a 15 MB cart wouldn't really have made economic sense.


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