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PostPosted: Wed Nov 21, 2018 4:00 pm 
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I've mentioned this idea a couple of times in other contexts, but it didn't generate any discussion, and I'm kinda curious about whether I'm right. I might even need it, although I'm still hoping I won't...

...

As we know from the adventures of Drakon and his trusty glue gun, Super FX chips can be overclocked a fair bit. Of course, the practical limit varies between units, and in any case it seems unlikely that Nintendo would have approved of a licensed developer attempting to deploy a 60 MHz MARIO Chip 1. But what if a GSU2 could be overclocked in a way that left it completely within spec?

If bus access time for the Super FX reflects the memory speed in the same way as the timing of the second half-cycle of the S-CPU's bus access, then the five-cycle byte access time in fast mode implies the use of 200 ns memory. The fact that Super FX games are invariably described as SlowROM lends some weight to this assumption. It would seem to make sense that the use of cheaper memory would have been assumed in connection with an expensive coprocessor, especially early in the console's life when the Super FX was being developed.

But there doesn't seem to be a FastROM variant of the Super FX. With 120 ns memory, if my assumption above is accurate, bus access could be reduced to three cycles per byte in fast mode, which would substantially speed up blitting, texture mapping, RAM reads, and really just about anything that uses the external buses heavily enough for the access time to be a bottleneck. Unfortunately it seems this was never done.

Here's the thing: in slow mode (nominally 10.7 MHz on a 21.4 MHz crystal), bus access is three cycles per byte rather than five, and as far as I know that's the only timing difference between the modes. So why not simply leave the chip in slow mode, with fast multiply turned off, and feed it a 42.8 MHz clock signal? That should give you a 21.4 MHz Super FX chip with 3-cycle bus access, right? And if you were to use 120 ns ROM and SRAM, everything (except possibly the clock divider?) would be within spec.

Am I missing something?


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PostPosted: Wed Nov 21, 2018 10:06 pm 
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You are taking care of not overclocking the ROM and SRAM chips, but you seem to have forgotten the GSU chip itself, which might also dislike overclocking. For example, the caches are supposedly already using the maximum speed, anything faster won't be within specs.


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PostPosted: Wed Nov 21, 2018 10:35 pm 
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I'm not forgetting the GSU. The whole point here is that the chip has a setting that makes it run at half speed. That includes the instruction cache, or at least execution out of it. Are you saying that the pixel caches operate at 21 MHz regardless of that setting? Would that include the MARIO chip? What was the purpose of the slow mode in the first place?

IIRC, Drakon said he could get much higher overclocks by leaving the chip in slow mode. This suggested to me that the most timing-sensitive parts might not care what the master clock is, only the core clock.


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PostPosted: Wed Nov 21, 2018 11:02 pm 
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Most of the time when I heard people talking about overclocking the GSU, it seemed that they often doubled the external clock and enabled the divider—something that I would naively assume would result in similar performance to the normal 22MHz clock without the divider.

(I definitely saw instances of getting faster performance than that too, but I was never certain whether the "we went from 22MHz to 55MHz" actually meant anywhere near a 2.5x improvment, or if it was really much closer to 1.25x)


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PostPosted: Wed Nov 21, 2018 11:08 pm 
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93143 wrote:
I'm not forgetting the GSU. The whole point here is that the chip has a setting that makes it run at half speed.

Oops, okay, then it makes more sense.

What about the bus-sharing for SNES and GSU both reading ROM? If the 5 cycles for a GSU read include the time needed for a SNES read occurring simultaneously, then the ROMs might be already faster than you think. Though you might overcome that by using yet faster ROMs than Nintendo might have used.

Without having official specs on GSU overclocking it's hard tell what is within specs. Best you could do would be finding a configuration that works insanely fast - and then, say, declare half that speed as "safe" limit (and do some checks if any chips are overheating).


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PostPosted: Wed Nov 21, 2018 11:28 pm 
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lidnariq wrote:
Most of the time when I heard people talking about overclocking the GSU, it seemed that they often doubled the external clock and enabled the divider—something that I would naively assume would result in similar performance to the normal 22MHz clock without the divider.

That's exactly what I'm talking about.

The difference between stock and what you're describing is that when the divider is enabled, the ROM and RAM buses are accessed in 3 core cycles (6 master cycles) instead of 5 core cycles (5 master cycles). So if you fed it a 43 MHz clock, with the divider on, it would run at 21 MHz but with 3-cycle bus access instead of 5-cycle bus access. This would speed up plotting, RAM reads, repeated RAM writes, ROM reads, and cache misses.

It would also involve operating ordinary 200 ns ROM out of spec, and possibly the RAM as well. But that seems like an easy thing to fix...

nocash wrote:
What about the bus-sharing for SNES and GSU both reading ROM?

The GSU doesn't do that. You're thinking of the SA-1.

...and I just realized that I have to use a trampoline for my H-IRQ regardless of whether I use fast SRAM in the MMIO area or not, because the value of the IRQ vector is fixed at $010C while the GSU is running. Nuts...

Quote:
Without having official specs on GSU overclocking it's hard tell what is within specs. Best you could do would be finding a configuration that works insanely fast - and then, say, declare half that speed as "safe" limit (and do some checks if any chips are overheating).

I'm trying to come up with a configuration that wouldn't be considered "cheating". Something a master negotiator could have convinced Nintendo to allow in a commercial cartridge, or perhaps it might be considered a way to emulate the FastROM GSU Nintendo could easily have had Argonaut make for them but never did.

So I don't actually want to drive the core any faster than the nominal 21 MHz or so, or use faster memory than the 120 ns that Nintendo already offered in different configurations. If even that is impossible to do reliably, so be it, but what I've seen of existing overclocking efforts is encouraging.

As you say, it's hard to tell. I don't know how much of the chip is exposed to the master clock, or whether there are components other than the bus handling logic that alter their behaviour based on the speed bit (I'm not aware of anything of that nature that's visible to the programmer - there is a "fast multiply" bit that you're only supposed to use in 10.7 MHz mode, but that's more of a counterexample). But there are people here who have a much more extensive knowledge of microelectronics than I do, and I'm still hoping for something a little more definite...


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