Yes, the term LoROM and HiROM generally refer to mode 20 and 21 memory mappings. These are dictated by the actual PCB itself (how Nintendo chose to run address/data lines, etc.). There are several "variations" of these, however, but there are also a very well-known set of standard board types. These correlate directly with the 65816's addressing space, i.e. "how" your ROM ends up being laid out in memory. The wiki page you referenced explains it, but is also extremely verbose -- Tepples made a visual that's easier to understand
(first = general map, 2nd = mode 20, 3rd = mode 21). Make sense?
Bank $00 on the 65816 is special because it's where direct page RAM always resides, where most MMIO registers are, and -- most importantly -- where the 65816/6502 vectors have to be (for RESET, NMI, IRQ, BRK, and COP) up in the $00FFxx area. The CPU always loads them out of bank $00. So you'll find that both mode 20 and mode 21 tend to ensure that at least 32KB of ROM ends up being at $008000-FFFF. Also make sense?
It looks like your assembler is generating 32KB banks, which means your ROM result is probably mode 20. That's fine! But adhering to mode 20, this means your ROM actually is mapped like this in to 65816 addressing space:
$008000-FFFF = WLA DA bank 0
$018000-FFFF = WLA DA bank 1
$808000-FFFF = WLA DA bank 0 (can use high speed/FastROM mode)
$818000-FFFF = WLA DA bank 0 (can use high speed/FastROM mode)
The advantage of this mode is that $xx0000-7FFF is identical throughout most of the banks (there are some exceptions), which means you can access MMIO registers while in any bank without any problem (i.e. lda #$86 / pha / plb / lda $94f2 / sta $2100
will work exactly how you think).
The "high speed/FastROM" mode I describe is relevant when you're using those banks/addressing ranges and have $420D bit 0 set to 1. In that situation, things there execute at 3.58MHz, rather than the usual 2.68MHz elsewhere.
Mode 21 is an entirely different beast, where there's a similar mode 20 layout for banks $00-3F, and again for banks $80-BF. However, banks $C0-FF are completely different: here your ROM is completely 100% linear and in 64KByte banks (which is the normal size of a bank on 65816). I could tell you how WLA DX implemented support for this if I had tried it, but I suspect it might be something like this:
$008000-FFFF = WLA DX bank 0 (first 32KB)
$018000-FFFF = WLA DX bank 0 (next 32KB)
$808000-FFFF = WLA DX bank 0 (first 32KB) (can use high speed/FastROM mode)
$818000-FFFF = WLA DX bank 0 (next 32KB) (can use high speed/FastROM mode)
$C00000-FFFF = WLA DX bank 0 (full 64KB)
$C10000-FFFF = WLA DX bank 1 (full 64KB)
Make sense? (Probably not)
As for your follow-up question about long addressing:
Correct, long (24-bit) addressing takes 1 additional CPU cycle. It's impossible for me to answer whether or not it could be "detrimental" to your program because I don't know your program -- you're the author, and I don't think it would be fair to ask me to review your entire program for optimisations/profiling.
If you have a routine that is being executed in a timing-sensitive area (such as NMI or HBlank), places where every CPU cycle counts, then you need to take this into consideration.
Just remember that the "setup" (sep/lda/pha/plb
) and the "restore" (plb
, possibly with a sep
) take cycles too, so depending on what you're doing + how much data + whatever, it may be faster to use long addressing. If you aren't sure, count the cycles yourself by hand.
In other cases -- take for example what I just showed you about mode 21, think about code running out of banks $C0-FF -- you're going to have to use long addressing to access MMIO registers (e.g. sta $002100
). There are magic tricks to avoid that though, depending on what you are doing (particularly how much MMIO register access you might be doing). A technique I've seen used in commercial games (just as an example for screen brightness) is rep #$20 / tdc / pha / lda #$2100 / tcd / sep #$20 / lda #$0f / sta $00 / ... / rep #$20 / pla / tcd
. This points D (direct page) to $2100, which is at the start of the MMIO register area; the sta $00
thus writes to $2100, with backing up and restoration of the D register. You obviously can't access your own direct page variables in the midst of that, though.
Like I said: it's impossible to cover every situation.
Hope this helps.