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PostPosted: Thu Jan 24, 2019 8:03 am 
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Hello everyone! Longtime lurker, first time post.

I am working on reverse engineering a SNES cartridge as a personal project to learn a bit more about how the system works. For the most part, I understand how the cartridges work, with the exception of the MAD-1 chip/74139 seen on earlier boards. This chip should be a decoder to tell when the SNES wants to work with the ROM or the SRAM, and enable the corresponding chip. I am confused though- it seems that the connector pinout has pin 49 for ROM /OE (/CART) and pin 54 for RAM /OE (/WR). These lines should both be high and then dropped when the system wants to read from the respective chip. What is the purpose of the decoder chip then? I understand it's use for games with multiple ROM, but for games without it, I can't understand the purpose, especially since it's connected to RAM /CE, which I thought that p54 was dedicated to doing.

From romlabs, I also saw that some of the pins of the MAD-1 are connected to A21, A22- what is the reason for this? Are those connections related to the operation of the decoder? Is the SNES sending hardware requests on those lines?

Thanks for all the help and knowledge nested on these forums!


Last edited by VIP Quality Post on Thu Jan 24, 2019 9:31 am, edited 1 time in total.

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PostPosted: Thu Jan 24, 2019 8:23 am 
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As a note, I see a lot of this diagram passed around, originating from warosu, some online board Image
The connections for the 74139 kind of make sense, with /WR used to enable writes on the RAM, and /RD for /OE on ROM and RAM. However, I've seen some users here say that this diagram isn't necessarily correct, so I'm not sure if this is a good resource to use. I'm also confused by the stray caps littered around the board- are these for buffering the power to the chips when the system is reset/powered off? What other purpose do they serve? With some of them at 70nF, I can't imagine they're particularly useful.


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PostPosted: Thu Jan 24, 2019 8:32 am 
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Location: NE Indiana, USA (NTSC)
How I interpret Game Pak slot pin descriptions from Fullsnes:

  • Pin 49 is ROM select. This is low when the address bus is pointed anywhere in the upper half of banks $00-$3F and $80-$BF and all of banks $40-$7D and $C0-$FF.
  • Pin 54 is write. This is low when the CPU is writing anywhere, including to peripherals in conventionally "ROM" space and (I think) internal WRAM.
  • There is no pin dedicated to enabling cartridge RAM, which in HiROM games is conventionally located at $3x6000-$3x7FFF and in LoROM games is conventionally in bank $70.

Yes, the "bypass capacitors" or "decoupling capacitors" are for stripping AC transients out of the DC power supply. You usually see 100 nF of decoupling near each IC's +5V pin and tens to a few hundred μF near the edge connector.


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PostPosted: Thu Jan 24, 2019 8:42 am 
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Okay, so since there is no pin dedicated to enabling cartridge RAM, we use the decoder to enable RAM when pointing at external WRAM space, and this is done on A21 and A22?

Also, what do you mean when writing to 'conventionally "ROM" space'- are you referring to the cartridge, or the ROM itself? I was under the impression there were no writable areas in ROM- hence read-only.

Thanks for the tip on the capacitors!


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PostPosted: Thu Jan 24, 2019 8:46 am 
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The circuit generating the ROM select signal at the cartridge edge doesn't know whether the memory behind that address is ROM, RAM, or MMIO. Take the SNES PowerPak for example: it emulates ROM using RAM by first copying an executable from the CF card into RAM. In addition, some coprocessors are mapped in parts of ROM space.


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PostPosted: Thu Jan 24, 2019 9:17 am 
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I understand the purpose of the chip now. I think I just had some core misunderstandings on the edge connector roles.

Regarding the role of specific address pins in enabling/disabling the ROM and RAM, do you have any ideas about why those pins (A21/A22) are used for controlling the decoder?

Additionally, I remembered seeing this image a while ago which was on a short tutorial, so no explanation was given as to why they were tying the ROM /CE to A0 (or both demux as well, for that matter). Does that have to do with the fixed top of the stack pointer (https://youtu.be/fWqBmmPQP40?t=399) since A0 will always be low? Similarly, can a trend be found between wanting to read/write data to the RAM/ROM and toggling A21/A22?


Last edited by VIP Quality Post on Thu Jan 24, 2019 9:22 am, edited 1 time in total.

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PostPosted: Thu Jan 24, 2019 9:17 am 
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Forgot image: Image


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PostPosted: Thu Jan 24, 2019 11:51 am 
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Location: Seattle
VIP Quality Post wrote:
Regarding the role of specific address pins in enabling/disabling the ROM and RAM, do you have any ideas about why those pins (A21/A22) are used for controlling the decoder?
Different boards used different conventions for where one could address ROM or RAM. The specific address lines correspond to how the PCB is laid out, and where the ROM is programmed to expect to find ROM and RAM.

There's nothing magical specifically about A21 and A22.

VIP Quality Post wrote:
so no explanation was given as to why they were tying the ROM /CE to A0
That is not what's depicted...

Quote:
(or both demux as well, for that matter).
The 27C322 always has a 16-bit wide data bus. The SNES cannot use this, it only has an 8-bit wide data bus.

The 74'157 multiplexers take the 16 bits out of the ROM and selects one half or the other for the SNES, according to A0.


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