jwiggams wrote: ↑
Wed Aug 05, 2020 12:16 pm
So what would it look like if accessing that region?
Address bus is stable, /WR or /RD falls, data bus must be valid by rising edge.
Should I even be clocking on the edges of these signals, or just look for nRD being high and nWR being low, while accessing the address I need?
Choosing between a synchronous design or an asynchronous design is up to you. As I understand it, most PLDs synthesize synchronous designs better... but I could be wrong.
Also, when should the data from a write be valid? Should I be grabbing the value as soon as nWR goes low, or wait for x amount of time before getting it?
Looking at the logic analyzer traces
we have of a SNES, the data bus is driven at the same time that /WR falls, but it might not be valid in time. All the ones in those traces show the data bus goes from undriven to driven at the same sampling time that /WR goes from high to low.
The 65816 datasheet vaguely insinuates that the data bus is probably not ready when /WR falls (but it's hard to tell, because unlike the SNES the 65816 multiplexes A16-A23 using the data bus, so it obviously can't have valid data contents at that time)