SNES mapper testing

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jwiggams
Posts: 9
Joined: Mon Feb 20, 2017 12:44 pm

SNES mapper testing

Post by jwiggams » Wed Aug 05, 2020 11:44 am

I'm working on a custom mapper project for SNES electronics project to control some LEDs, using $2200-3FFF range. I've got a test ROM that you can put an address in, and write a byte value to that address. When I do this, things mostly don't work (LEDs either don't come on or have wrong state) - meaning the byte values are wrong or never received.

What should the nCS, nRD and nWR pins be doing normally during access to these regions? I figured it would be something like:

Code: Select all

//when accessing $2200-3FFF nCS should be high?
always @ (posedge nCS) begin

//write should go low if sending byte value to cart
if (nWR == 0) begin

//if the address is what we expect, send byte to led array reg
if (address_in ==24'h802200)
LED_array <= data_in;
But as mentioned, the above doesn't work. Can anyone help steer me in the right direction?

- John

lidnariq
Posts: 9659
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: SNES mapper testing

Post by lidnariq » Wed Aug 05, 2020 12:04 pm

jwiggams wrote:
Wed Aug 05, 2020 11:44 am
//when accessing $2200-3FFF nCS should be high?
always @ (posedge nCS) begin
"nCS" is not an edge in the SNES. You have to clock your behavior, if you're using edge logic, on /RD or /WR (or PAWR or PARD) as appropriate.

(nCS in the SNES is literally just a function of the address bus, lines A23-A17 and A15)

jwiggams
Posts: 9
Joined: Mon Feb 20, 2017 12:44 pm

Re: SNES mapper testing

Post by jwiggams » Wed Aug 05, 2020 12:16 pm

lidnariq wrote:
Wed Aug 05, 2020 12:04 pm
"nCS" is not an edge in the SNES. You have to clock your behavior, if you're using edge logic, on /RD or /WR (or PAWR or PARD) as appropriate.

(nCS in the SNES is literally just a function of the address bus, lines A23-A17 and A15)
So what would it look like if accessing that region? Should I even be clocking on the edges of these signals, or just look for nRD being high and nWR being low, while accessing the address I need?

Also, when should the data from a write be valid? Should I be grabbing the value as soon as nWR goes low, or wait for x amount of time before getting it?

lidnariq
Posts: 9659
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: SNES mapper testing

Post by lidnariq » Wed Aug 05, 2020 12:45 pm

jwiggams wrote:
Wed Aug 05, 2020 12:16 pm
So what would it look like if accessing that region?
Address bus is stable, /WR or /RD falls, data bus must be valid by rising edge.
Should I even be clocking on the edges of these signals, or just look for nRD being high and nWR being low, while accessing the address I need?
Choosing between a synchronous design or an asynchronous design is up to you. As I understand it, most PLDs synthesize synchronous designs better... but I could be wrong.
Also, when should the data from a write be valid? Should I be grabbing the value as soon as nWR goes low, or wait for x amount of time before getting it?
Looking at the logic analyzer traces we have of a SNES, the data bus is driven at the same time that /WR falls, but it might not be valid in time. All the ones in those traces show the data bus goes from undriven to driven at the same sampling time that /WR goes from high to low.

The 65816 datasheet vaguely insinuates that the data bus is probably not ready when /WR falls (but it's hard to tell, because unlike the SNES the 65816 multiplexes A16-A23 using the data bus, so it obviously can't have valid data contents at that time)

jwiggams
Posts: 9
Joined: Mon Feb 20, 2017 12:44 pm

Re: SNES mapper testing

Post by jwiggams » Wed Aug 05, 2020 1:23 pm

Address bus is stable, /WR or /RD falls, data bus must be valid by rising edge.
Got it! I had thought that nCS was needed because it's low when accessing the ROM space and as such would be high whenever I was accessing the $2200-3FFF range, but I've since changed my code to clock on the rising edge of nWR and now things seem to be working much better.

Thanks for your help!

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