SNES jitter

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Oziphantom
Posts: 913
Joined: Tue Feb 07, 2017 2:03 am

SNES jitter

Post by Oziphantom » Tue Aug 11, 2020 9:53 am

I've have some issues with IRQ jitter, while I know how to fix it, the 65816 makes it trivial, but I still don't understand why I need to do so much. ( 2 lines )

Something causes the IRQ to be delayed up to a line. Which is well beyond the 0-8 clocks you get thanks to the IRQ only interrupting in the read state of an instruction. What on the SNES can cause such massive delays. Nothing DMA stalls the 65816. Does an MVN MVP instruction halt until the entire operation is completed?

calima
Posts: 1186
Joined: Tue Oct 06, 2015 10:16 am

Re: SNES jitter

Post by calima » Tue Aug 11, 2020 10:08 am

Each byte moved takes 7 cycles. MVN and MVP can be interrupted by IRQ and NMI before the move is complete (unlike every other instruction, which must finish before an IRQ or NMI is serviced); however, they can only be interrupted every seventh cycle, i.e. they cannot be interrupted in the middle of moving a byte, but it can be interrupted between moving one byte and moving the next.
http://6502.org/tutorials/65c816opcodes.html#6.6

Oziphantom
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Joined: Tue Feb 07, 2017 2:03 am

Re: SNES jitter

Post by Oziphantom » Tue Aug 11, 2020 10:12 am

ok so not a MVN/P instruction doing it then.

93143
Posts: 1225
Joined: Fri Jul 04, 2014 9:31 pm

Re: SNES jitter

Post by 93143 » Tue Aug 11, 2020 1:32 pm

I have no idea. I've done a bit of IRQ stabilization in my day, and I've never had to give it more than you'd think it would need based on instruction length.

However, it should be noted that my DMA direct colour demo displays one line down from where it should be in higan/bsnes. It works properly on real hardware. We never did figure out why this was happening...

turboxray
Posts: 104
Joined: Thu Oct 31, 2019 12:56 am

Re: SNES jitter

Post by turboxray » Mon Aug 17, 2020 10:42 am

Oziphantom wrote:
Tue Aug 11, 2020 9:53 am
I've have some issues with IRQ jitter, while I know how to fix it, the 65816 makes it trivial, but I still don't understand why I need to do so much. ( 2 lines )

Something causes the IRQ to be delayed up to a line. Which is well beyond the 0-8 clocks you get thanks to the IRQ only interrupting in the read state of an instruction. What on the SNES can cause such massive delays. Nothing DMA stalls the 65816. Does an MVN MVP instruction halt until the entire operation is completed?
Isn't work ram refresh 40 cycles ever scanline? I would guess that if you access ram while this is happening, that /RDY is asserted (or whatever the equivalent is on the SNES setup).

Oziphantom
Posts: 913
Joined: Tue Feb 07, 2017 2:03 am

Re: SNES jitter

Post by Oziphantom » Mon Aug 17, 2020 10:05 pm

clockSlide.png
clockSlide.png (5.37 KiB) Viewed 999 times
The bottom most Red dot is the nominal position, but as you can see the IRQ can slide almost the whole line. Sometimes it is less
clockSlide2.png
clockSlide2.png (6.24 KiB) Viewed 999 times
most of the time it is in the grey area with the odd flick into the display.

93143
Posts: 1225
Joined: Fri Jul 04, 2014 9:31 pm

Re: SNES jitter

Post by 93143 » Tue Aug 18, 2020 1:47 am

Hang on - you're using a bunch of DMA during active display, aren't you? I don't believe an IRQ can interrupt a DMA...

Oziphantom
Posts: 913
Joined: Tue Feb 07, 2017 2:03 am

Re: SNES jitter

Post by Oziphantom » Tue Aug 18, 2020 2:18 am

ah I see, I figured since I had all DMA ticked in event viewer it would show me the DMAs, but playing around with it, yes there are WRAM DMAs happening. Which does explain the IRQ delay.

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