Question about rendering pipeline / disabled Windows

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LilaQ
Posts: 29
Joined: Mon Sep 02, 2019 3:28 pm

Question about rendering pipeline / disabled Windows

Post by LilaQ » Sun Oct 04, 2020 8:51 am

Hi guys,

I'm currently working on implementing the PPU for my SNES emulator. I was working off of this screenshot:
PPU logic.png
which comes from the great RetroGameMechanicsExplained video regarding Color Math (timestamp): https://youtu.be/zcoU6-9_fDM?t=219

He says that when both windows are disabled, all pixels are automatically considered inside the window (timestamp). But the schematic doesn't show this. Is there something missing in the schematic, or am I understanding something wrong here?

I would assume that the statement is true, since I just saw a demo (for debugging purposes) with both windows disabled (no inversion, OR-ed)

If someone could explain this to me I would be really thankful, so I could finalize the pipeline :)

Thanks a lot in advance!

LilaQ

creaothceann
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Re: Question about rendering pipeline / disabled Windows

Post by creaothceann » Sun Oct 04, 2020 5:12 pm

See the window registers here.
My current setup:
Super Famicom ("2/1/3" SNS-CPU-GPM-02) → SCART → OSSC → StarTech USB3HDCAP → AmaRecTV 3.10

LilaQ
Posts: 29
Joined: Mon Sep 02, 2019 3:28 pm

Re: Question about rendering pipeline / disabled Windows

Post by LilaQ » Sun Oct 04, 2020 7:35 pm

I'm aware of Anomie's and no$'s docs, yet I still don't see where it fits in that diagram :/

calima
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Re: Question about rendering pipeline / disabled Windows

Post by calima » Mon Oct 05, 2020 12:12 am

Perhaps that's the programmer's view. Both disabled = all pixels shown. Not particularly relevant to programmers how it's wired in hw.

LilaQ
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Joined: Mon Sep 02, 2019 3:28 pm

Re: Question about rendering pipeline / disabled Windows

Post by LilaQ » Mon Oct 05, 2020 6:11 am

Well, to me it is, or at least could be. Since if I knew the complete rendering pipeline and how it's wired, I could possibly take shortcuts (for performance) and still be precise.

If I'm not mistaken it would somehow have to bypass the WinLog unit (where the X/N/OR operations happen) - or get completely inversed somewhere at the start.

LilaQ
Posts: 29
Joined: Mon Sep 02, 2019 3:28 pm

Re: Question about rendering pipeline / disabled Windows

Post by LilaQ » Mon Oct 05, 2020 4:57 pm

Update: I was fortunate enough to get a response from the RGME creator, so I will share it here, in case someone is interested in this in the future:
When W1En and W2En are both false, the output of the block above WinLog is forced to be false. (That is, the state of WxIO and WinLog doesn't matter.) This means the input to the blocks by the Main/SubSW have false as an input, so the four outputs could be true, false, true, false. Additionally, the two unnamed switches on the layer data between the Priority Circuits and the TM/TS switches are forced to be closed. (That is, the state of TSW and TMW don't matter.)

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