Searching an expert to find compressed bmp files in a SNES bin file

[maxibolide]

Hello everyone

I'm really sorry to bother you but I searching someone who could help me in a quest of finding the location of some compressed image files in a .bin file ^^.

The file that is question about is the GROM (1,2,3 or 4) of the Super Famicom Box. The compressed image is the game banners in the main menu. I know that each game points to its banner at adress $X04F (where X could be 1,2,3 ou 4 depending on the game) but after that, I've no idea where to continue my researches ...

If there's someone who's motivated to help me in my quest, I would be very happy and thankfull . The main goal would be to be able to add a custom banner to my added game ^^.

Thanks in advance

[nocash]

Do you mean the compressed bitmaps described here https://problemkaputt.de/fullsnes.htm#sfcboxgromformat ?
But then, what is unclear about their location?

[maxibolide]

Do you mean the compressed bitmaps described here https://problemkaputt.de/fullsnes.htm#sfcboxgromformat ?
But then, what is unclear about their location?

Thanks nocash I didn't knew the existence about this website ^^ . It'll help me a lot . The main problem was that I didn't knew where to find them to replace them ^^

[maxibolide]

Hi nocash ,

I wanted to thank you for giving me some help in my researches on the SFBox and also for the amazing work that you've done so far on documenting that device !! Really thank you !! .

I also wanted to ask you if you could maybe help me on trying to make work 6 different roms on a single PSS cartridge ^^. So far, I've been only able to add 1 game to a PSS-64 cartridge on slot ROM5 (bottom-left). I've tried many things to make run a second added game on slot ROM12 but nothing worked... (tried to modify the GALS values, adding a random value for the added game on the GROM header, but none...

Thanks again

[nocash]

Glad that it helped for adding one ROM!
With more ROMs, what is the problem... the game not working, or the game not even showing up in the menu?
For testing, you can emulate the stuff in no$sns (if you merge all ROMs from one (or two) PSS carts all in one file).
I am not sure if the emulation is accurate on uncommon memory mappings.

[maxibolide]

Glad that it helped for adding one ROM!
With more ROMs, what is the problem... the game not working, or the game not even showing up in the menu?
For testing, you can emulate the stuff in no$sns (if you merge all ROMs from one (or two) PSS carts all in one file).
I am not sure if the emulation is accurate on uncommon memory mappings.

Thank you for your reply . The main problem is that the game shows up but doesn't boot when selected. I don't know which value to use for rom slots 2,4,8,10 and if I have to change some lines in the GAL CHIP (and in that case, what value to use) ^^' .

I didn't tried yet the no$sns emulator but think that I'll soonly use it ^^ .


Thanks again

[nocash]

I would hope that the mapping is done soley via GROM, not needing to use different GALs (unless you know of different GALs, like PSS61 gal being incompatible with PSS64).

The values in GROM are passed to the small Z80 function (which is also in GROM), maybe you need to reprogram that function for some confiigurations.

The port [C0h] mapping register is more or less clearly supprting only 2bits for selecting max 4 different ROMs (unless it is combined with other bits elsewhere).

Going by that register, ROM1/7/12 seem to share the same chip select (for whatever reason, maybe with different wiring for ROM vs EPROM and LoROM vs HiROM etc). Best check if they are really all wired to the same chip select signal (if you have the real PCB and a multimeter).

EDIT: And, probably there is also support for games that use two ROM chips for a single game. I rather don't think that the six ROMs solder are intended for six different games. But I don't have the real hardware myself - maybe you can find out more when drawing a schematic or tracing the cartridge slot pinouts.

[maxibolide]

I would hope that the mapping is done soley via GROM, not needing to use different GALs (unless you know of different GALs, like PSS61 gal being incompatible with PSS64).

By adding a 4th game on slot ROM12 on PSS-64, by just modifying correctly the GROM, game 3 doesn't boot no more. To still make the 3th game work with a 4th game on the PCB, I had to modify the value on the GAL on adress 1280 (1024 and 1280 have the same value in the PSS-64 GAL). So I supposed that something needed to be changed in the GAL but I'm probably wrong ^^.

The values in GROM are passed to the small Z80 function (which is also in GROM), maybe you need to reprogram that function for some confiigurations.

The port [C0h] mapping register is more or less clearly supprting only 2bits for selecting max 4 different ROMs (unless it is combined with other bits elsewhere).

Going by that register, ROM1/7/12 seem to share the same chip select (for whatever reason, maybe with different wiring for ROM vs EPROM and LoROM vs HiROM etc). Best check if they are really all wired to the same chip select signal (if you have the real PCB and a multimeter).

EDIT: And, probably there is also support for games that use two ROM chips for a single game. I rather don't think that the six ROMs solder are intended for six different games. But I don't have the real hardware myself - maybe you can find out more when drawing a schematic or tracing the cartridge slot pinouts.

If the 2bits limitation is the answer, I should probably stop now searching a solution ^^. I should really try to start using the no$sns rather than the realy hardware to do some test...

If I can help you in a way with the real hardware, let me know

[nocash]

What I've used for rev-engineering was GROM and KROM disassemblies, and very low quality PCB photos. That leaves a lot of missing info in fullsnes.htm. Some info that would be nice to have...

SFC-Box Component List's for Cartridges & Console
The "unknown" chips in the two Component List chapters didn't have legible part numbers on the photos. Would be cool if you could update the missing stuff in component lists (or make better PCB photos).

Pinouts
Pinouts would be very cool (something like the "SNES Pinouts" chapters at the end of fullsnes.htm). Especially for the 100pin cartridge slot. Half of the pins are probably just wired to the CPUs and memory chips, which would make it easy (though time consuming) to trace them on the PCB. Well, and the other half, some might be VCC/GND, and some must be for custom mapping logic (to figure out what they are doing, one would probably also need to trace the pinouts of various logic chips).

GAL
That sounds interesting, too. Did you dump the GAL from the PSS64 cartridge, and/or from other PSS carts, too? I've mostly considered the GAL as unimportant gluework, but if they can be reprogrammed to enable more ROMs then they are apparently more useful.
- Do PSS61, PSS62, PSS63, PSS64 carts have different GAL contents?
- Any chance to get hold of the GAL dumps?
- Or better: The GAL binary converted to "source code style" logic functions?
- Well, and the GAL pinout/wiring would be also needed to make sense of the logic.

2bit Limit
That 2bit limit isn't carved in stone. It's related to the Z80 function in GROM. The incoming ROM Socket value at [BC+1] could be 8bit (or 7bit?) wide, so that would allow to use a lot of ROMs.

The GROM Z80 function is writing the lower 2bit of ROM Socket value to Port [C0h], hence the 2bit limit. The other bits appear to be written to Port [C0h], too - but those bits are overlapping with the SRAM/DSP bits, though it might be possible to share that bits for ROM socket selection.
With a custom cartridge PCB and customized GROM Z80 function one could do almost anything, like writing 8bit wide ROM Socket to a new mapper register at port C2h, and using ROM address pins from game selection (eg. allowing 12 games in one ROM chip, etc.).

The hard limit is probably the amount of ROMs supported by the GUI menu (though one could also write a custom GUI to bypass that). I don't know how many games are supported, as far as I remember it does support some sort of scrolling or next/prev page buttons for displaying more than 5 games.

[maxibolide]

Hello ^^ sorry for the late reply and Merry Christmas with 3 days of delay ^^ .

What I've used for rev-engineering was GROM and KROM disassemblies, and very low quality PCB photos. That leaves a lot of missing info in fullsnes.htm. Some info that would be nice to have...

I can't believe that you did this amassing job without the real hardware Well done ^^ .

SFC-Box Component List's for Cartridges & Console
The "unknown" chips in the two Component List chapters didn't have legible part numbers on the photos. Would be cool if you could update the missing stuff in component lists (or make better PCB photos).

I'll give you the photos in this message so that you could look by yourself . Before that I start, IC14 could also be EPL16P8BP but it does EXACLTY the same thing as the GAL16V8B (except that I don't know how to dump the EPL). The EPL could be mainly found in a PSS61 and PSS62 cartridge but I've found some PSS61 with GALS. Anyway, EPLs can be without any problems be replaced with GALs.

SFC-Box Component List (Cartridges)

IC5 : Motorola 74HC00A 406TY
IC6 : Motorola 74HC86 407IH
IC7 : Motorola 74HC32A 411B0
IC8 : Motorola 74HCa38A 408QP
IC9 : Motorola 74HC138A 408QP
IC10 : Motorola 74HC138A 408QP
IC11 : Motorola 74HC138A 408QP
IC12 : Motorola 74HC157A 407BP
IC22 : Motorola 74HC86 407IH
IC23 : Motorola 74HC08A 410BL
X1 : [M] ? 7600A 44 1

SFC-Box Component List (Console) :

U10 : 35BV LM 358M
U11 : 35BV LM 358M

Pinouts
Pinouts would be very cool (something like the "SNES Pinouts" chapters at the end of fullsnes.htm). Especially for the 100pin cartridge slot. Half of the pins are probably just wired to the CPUs and memory chips, which would make it easy (though time consuming) to trace them on the PCB. Well, and the other half, some might be VCC/GND, and some must be for custom mapping logic (to figure out what they are doing, one would probably also need to trace the pinouts of various logic chips).

I don't know how to help you here other than give you some pictures of the unit and the cartridges ^^' let me know what part you specially need .

GAL
That sounds interesting, too. Did you dump the GAL from the PSS64 cartridge, and/or from other PSS carts, too? I've mostly considered the GAL as unimportant gluework, but if they can be reprogrammed to enable more ROMs then they are apparently more useful.
- Do PSS61, PSS62, PSS63, PSS64 carts have different GAL contents?
- Any chance to get hold of the GAL dumps?
- Or better: The GAL binary converted to "source code style" logic functions?
- Well, and the GAL pinout/wiring would be also needed to make sense of the logic.

Yes I've dumped all the GROMs of my PSS cartridges (PSS61,PSS63 and PSS64) (I didn't find a PSS62 with a GAL (only EPL)). The values in PSS61 are different from the others (GALs of PSS63 and PSS64 are the same. I've replaced the EPL from the PSS62 with a GAL containing the same code of PSS63 and 64 and worked perfectly). I only managed to have the binary code of the gals but the content is really small (the IC size is 2194 Bits).

How can I send you the different GAL dumps ?

2bit Limit
That 2bit limit isn't carved in stone. It's related to the Z80 function in GROM. The incoming ROM Socket value at [BC+1] could be 8bit (or 7bit?) wide, so that would allow to use a lot of ROMs.

The GROM Z80 function is writing the lower 2bit of ROM Socket value to Port [C0h], hence the 2bit limit. The other bits appear to be written to Port [C0h], too - but those bits are overlapping with the SRAM/DSP bits, though it might be possible to share that bits for ROM socket selection.
With a custom cartridge PCB and customized GROM Z80 function one could do almost anything, like writing 8bit wide ROM Socket to a new mapper register at port C2h, and using ROM address pins from game selection (eg. allowing 12 games in one ROM chip, etc.).

The hard limit is probably the amount of ROMs supported by the GUI menu (though one could also write a custom GUI to bypass that). I don't know how many games are supported, as far as I remember it does support some sort of scrolling or next/prev page buttons for displaying more than 5 games.

I honestly don't know how I could reprogram that function without breaking something in the logical process of the unit ^^' . If you know how to do it, I would be really interested to see how you'd do it ^^.

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[nocash]

Thanks for the component lists and photos. And good to know that the GAL could be EPL16P8BP or GAL16V8B, and that the PSS51 cart does actually have different logic stored in the GAL.

How can I send you the different GAL dumps ?

Post them here as attachment? Unless you are worried about copyright issues (I think copyright isn't much of an issue for that kind out of production logic chips).
I've no idea how to disassemble the GAL binary into source-code-style logic functions, I hope somebody in the forum knows how to do that...

Pinouts would be very cool

I don't know how to help you here

If you want to spend some hours on it: Start using a multimeter to search 0 ohm connections between the CPU pins and cartridge slot pins. The pinouts for the SNES CPU are well known (the Z80 HD64180RF6 chips are probably also documented somewhere), and the trick is simply to find out which pins on the cartridge slot they do connect to.

If you want to cheat: The WRAM and ROM chips have bigger solder pads, so it may be easier to use that pins instead of the CPU pins (and hope that D0..D7 and A0..A14 are actually wired to the corresponding CPU pins) (on the other hand, with LoROM carts, it's well known that ROM.A15 and up do NOT directly correspond to CPU.A15 and up).

The GROM Z80 function is writing the lower 2bit of ROM Socket value to Port [C0h]...

I honestly don't know how I could reprogram that function

That isn't very difficultl. The whole GROM code contains only 150 lines of code (and that is also including the SRAM mapping, the code for the ROM mapping is even smaller). But before changing the GROM code, you would first need to understand how the mapping logic working...
That would require knowing pinouts for cartridge slot, and the wiring of the GAL pins, and ROM chipselect pins... And to find the Port C0h/C1h latches that contain the mapping state. They might be somewhere on the main board, or are that two 74HC273 chips on each cartridge board? Wherever they are, their inputs should go to the Z80 databus, and their outputs should probably go to the GAL.

PS. Below is a disassembly of the PSS61 GROM opcodes. It's really simple and could be easily changed -- as long as you understand your mapping logic and know what values you want to write to which registers what for.

Code: Select all

Incoming paramters:
  A=function (00h=Change Mapping, FFh=Boot Callback, other=Reserved)
  BC=ptr to 10-bytes
  E=same as [BC+5]
  [BC+0]  ROM Slot (0 or 1)                                ;Cartridge Slot 0-1
  [BC+1]  ROM Socket (0..3)                                ;from GROM[8]
  [BC+2]  Mapmode (0=LoROM, 1=HiROM, 2=GSU)                ;from GROM[P0+16h]
  [BC+3]  Used Chipset (bit0=SRAM, bit1=DSP)               ;from GROM[P0+2Ah]
  [BC+4]  SRAM Size (0=None, 1=2K, 3=8K, 5=32K)            ;from GROM[P0+17h]
  [BC+5]  SRAM Base (0..3) (0..7 when 2 chips)             ;from GROM[P0+1Ch]
  [BC+6]  Slot 1 Chipset (bit0=SRAM, bit1=DSP, bit2=GSU?)  ;from Slot1.GROM[4]
  [BC+7]  Slot 0 Chipset (bit0=SRAM, bit1=DSP, bit2=GSU?)  ;from Slot0.GROM[4]
  [BC+8]  Copy of Port[C0h]  ;\the function must update these values alongside
  [BC+9]  Copy of Port[C1h]  ;/with the new values written to Port C0h/C1h

Port [C0h].W - SNES Mapping Register 0
  0-1 ROM Socket  (0=ROM5, 1=ROM1/7/12, 2=ROM3/9, 3=IC20)
  2   ROM Slot    (0=Slot0, 1=Slot1)
  3   SRAM Enable (0=Disable, 1=Enable)
  4   SRAM Slot   (0=Slot0, 1=Slot1)
  5   DSP Enable  (0=Disable, 1=Enable)
  6   DSP Slot    (0=Slot0, 1=Slot1)
  7   ROM, DSP, and/or SRAM Mapping (0=LoROM, 1=HiROM)

Port [C1h].W - SNES Mapping Register 1
  0-1 ROM, DSP, and/or SRAM Mapping (0=Reserved, 1=GSU, 2=LoROM, 3=HiROM)
  2-3 SRAM Base   (in 32Kbyte units) (range 0..3)
  4   GSU Slot    (0=Slot0, 1=Slot1)
  5   Zero/Unused?
  6-7 SRAM Size   (0=2K, 1=8K, 2=Reserved, 3=32K)

;------------------
                 grom_function_entrypoint:
0030 B7           or   a,a                 ;\
0031 28 01        jr   z,@@cont            ; exit if a<>00h
0033 C9           ret                      ;
                 @@cont:                   ;/
0034 DD 21 00 00  ld   ix,0000             ;\set ix=bc
0038 DD 09        add  ix,bc               ;/
003A DD 4E 00     ld   c,[ix+00]           ;-(c=[ix+0] for below)
003D DD 46 01     ld   b,[ix+01]           ;-b=ROM Socket (b=[ix+0]) (bit0-1)
0040 79           ld   a,c   ;=[ix+00]     ;\
0041 B7           or   a,a                 ; ROM Slot
0042 28 04        jr   z,@@cont2           ; if [ix+0]<>0 then b=b or 04h
0044 3E 04        ld   a,04                ;
0046 B0           or   a,b                 ;
0047 47           ld   b,a                 ;
                 @@cont2:                  ;/
                 ;- - -
0048 DD 7E 02     ld   a,[ix+02] ;(mapmode/speed)
004B DD 56 03     ld   d,[ix+03] ;(set/skip flags)
004E DD 6E 06     ld   l,[ix+06]
0051 FE 00        cmp  a,00
0053 28 08        jr   z,005D ;@@ix2_is_00h_or_03h_and_up
0055 FE 01        cmp  a,01
0057 28 0C        jr   z,0065 ;@@ix2_is_01h
0059 FE 02        cmp  a,02
005B 28 10        jr   z,006D ;@@ix2_is_02h
                 @@ix2_is_00h_or_03h_and_up:   ;\
005D 78           ld   a,b                     ; if [ix+2]=00h or [ix+2]>2
005E F6 00        or   a,00 ;blah              ;   b=b OR 00h  ;\LoROM
0060 47           ld   b,a                     ;   c=02h       ;/
0061 0E 02        ld   c,02                    ;
0063 18 18        jr   007D ;@@ix2_done        ;/
                 @@ix2_is_01h:                 ;\
0065 78           ld   a,b                     ; if [ix+2]=01h
0066 F6 80        or   a,80                    ;   b=b OR 80h  ;\HiROM
0068 47           ld   b,a                     ;   c=03h       ;/
0069 0E 03        ld   c,03                    ;
006B 18 10        jr   007D ;@@ix2_done        ;/
                 @@ix2_is_02h:                 ;\
006D 78           ld   a,b                     ; if [ix+2]=02h
006E F6 00        or   a,00 ;blah              ;   b=b OR 00h      ;\
0070 47           ld   b,a                     ;   if [ix+0]=00h   ; LoROM
0071 DD 7E 00     ld   a,[ix+00]               ;     c=01h  ;slot0 ; GSU
0074 B7           or   a,a                     ;   else            ;
0075 28 04        jr   z,007B ;@@set_c_01h     ;     c=11h  ;slot1 ;/
0077 0E 11        ld   c,11                    ;
0079 18 02        jr   007D ;@@ix2_done        ;
                 @@set_c_01h:                  ;
007B 0E 01        ld   c,01                    ;/
                 @@ix2_done:
                 ;- - -
007D 7A           ld   a,d   ;=[ix+03]
007E E6 01        and  a,01
0080 28 69        jr   z,00EB ;@@skip_part1 -----> skip SRAM part !!!
                 ;- - -
0082 7D           ld   a,l   ;=[ix+06]             ;\SRAM Slot Part I
0083 E6 01        and  a,01                        ;
0085 B7           or   a,a   ;blah                 ; If SRAM exists in
0086 28 04        jr   z,008C                      ; Slot1, then "default"
0088 CB E0        set  4,b                         ; to that slot
008A 18 02        jr   008E                        ;
                 @@                                ; B.Bit4 = [ix+6].Bit0
008C CB A0        res  4,b                         ;
                 @@                                ;/
008E CB D8        set  3,b                         ;-SRAM Enable (B.Bit3=1)
                 ;- - -
0090 7B           ld   a,e   ;=incoming "E=[ix+5]" ;\SRAM Slot Part II
0091 E6 04        and  a,04                        ;
0093 28 0E        jr   z,00A3 ;@@incoming_e_done   ; If SRAM bank 4..7,
0095 7D           ld   a,l   ;=[ix+06]  ;slot1     ; and SRAM exists in
0096 E6 01        and  a,01                        ; BOTH Slots, then
0098 28 09        jr   z,00A3 ;@@incoming_e_done   ; change above "default"
009A DD 7E 07     ld   a,[ix+07]        ;slot0     ; to Slot 0
009D E6 01        and  a,01                        ;
009F 28 02        jr   z,00A3 ;@@incoming_e_done   ;
00A1 CB A0        res  4,b                         ;
                 @@incoming_e_done:                ;/
                 ;- - -
00A3 DD 7E 04     ld   a,[ix+04]                   ;... SRAM size
00A6 FE 01        cmp  a,01
00A8 28 08        jr   z,00B2 ;@@ix4_is_01h_or_other_value
00AA FE 03        cmp  a,03
00AC 28 0A        jr   z,00B8 ;@@ix4_is_03h
00AE FE 05        cmp  a,05
00B0 28 0C        jr   z,00BE ;@@ix4_is_05h
                 @@ix4_is_01h_or_other_value:      ;\
00B2 CB B9        res  7,c                         ; if [ix+4]=01h (or 00h,02h,04h, or 06h..FFh)
00B4 CB B1        res  6,c                         ;  then C.Bit7-6 = 0
00B6 18 0A        jr   00C2 ;@@ix4_done            ;/
                 @@ix4_is_03h:                     ;\
00B8 CB B9        res  7,c                         ; if [ix+4]=03h
00BA CB F1        set  6,c                         ;  then C.Bit7-6 = 1
00BC 18 04        jr   00C2 ;@@ix4_done            ;/
                 @@ix4_is_05h:                     ;\
00BE CB F9        set  7,c                         ; if [ix+4]=03h
00C0 CB F1        set  6,c                         ;  then C.Bit7-6 = 3
                 @@ix4_done:                       ;/
                 ;- - -
00C2 DD 7E 05     ld   a,[ix+05]                   ;... SRAM base
                 ;GLITCH: should do "AND A,03" here (strip "SLOT"-bit)
00C5 FE 00        cmp  a,00
00C7 28 0C        jr   z,00D5 ;@@ix5_is_00h_or_other_value
00C9 FE 01        cmp  a,01
00CB 28 0E        jr   z,00DB ;@@ix5_is_01h
00CD FE 02        cmp  a,02
00CF 28 10        jr   z,00E1 ;@@ix5_is_02h
00D1 FE 03        cmp  a,03
00D3 28 12        jr   z,00E7 ;@@ix5_is_03h
                 @@ix5_is_00h_or_other_value:      ;\
00D5 CB 99        res  3,c                         ; if [ix+5]=00h (or 04h..FFh)
00D7 CB 91        res  2,c                         ;  then C.Bit3-2 = 0
00D9 18 10        jr   00EB ;@@ix5_done            ;/
                 @@ix5_is_01h:                     ;\
00DB CB 99        res  3,c                         ; if [ix+5]=01h
00DD CB D1        set  2,c                         ;  then C.Bit3-2 = 1
00DF 18 0A        jr   00EB ;@@ix5_done            ;/
                 @@ix5_is_02h:                     ;\
00E1 CB D9        set  3,c                         ; if [ix+5]=02h
00E3 CB 91        res  2,c                         ;  then C.Bit3-2 = 2
00E5 18 04        jr   00EB ;@@ix5_done            ;/
                 @@ix5_is_03h:                     ;\
00E7 CB D9        set  3,c                         ; if [ix+5]=03h
00E9 CB D1        set  2,c                         ;  then C.Bit3-2 = 3
                 @@ix5_done:                       ;/
                 ;- - -
                 @@skip_part1:
                 ;- - -
00EB 7A           ld   a,d   ;=[ix+03]             ;\
00EC E6 02        and  a,02                        ;  skipped if no DSP ?
00EE 28 0E        jr   z,00FE ;@@skip_part2        ;
00F0 7D           ld   a,l   ;=[ix+06]             ;
00F1 E6 02        and  a,02                        ; if [ix+3].Bit1=1
00F3 B7           or   a,a   ;blah                 ;   B.Bit6 = [ix+6].Bit1
00F4 28 04        jr   z,00FA                      ;   B.Bit5 = 1
00F6 CB F0        set  6,b                         ;
00F8 18 02        jr   00FC                        ;
                 @@                                ;
00FA CB B0        res  6,b   ;DSP slot             ;
                 @@                                ;
00FC CB E8        set  5,b   ;DSP enable           ;
                 @@skip_part2:                     ;/
                 ;- - -
00FE 78           ld   a,b                         ;\
00FF DD 77 08     ld   [ix+08],a                   ;
0102 ED 39 C0     out0 [C0],a                      ;/
0105 79           ld   a,c                         ;\
0106 DD 77 09     ld   [ix+09],a                   ;
0109 ED 39 C1     out0 [C1],a                      ;/
010C C9           ret

[maxibolide]

Post them here as attachment? Unless you are worried about copyright issues (I think copyright isn't much of an issue for that kind out of production logic chips).
I've no idea how to disassemble the GAL binary into source-code-style logic functions, I hope somebody in the forum knows how to do that...

Here they are. Yes I was a bit worried about copyright issues but if there is, I'll delete them immediately. Basically, the dump is a ".JED" but I've changed the extensions to .bin to attach them here. Don't forget to change them back to .JED .
The GAL should be logic gates I think. In the following link, there should be how a .JED file should look like (also included the equation file):

https://velesoft.speccy.cz/zx/umbrella/gal16v8-new.zip

There's already a tool that converts JED to equation : http://www.armory.com/~rstevew/Public/P ... GAL_Utils/ (the jed2eqn.exe is the one ). I'm not sure but I think that it only works on ms-dos. After that, you should have the equation. The most difficult part is to understand the equation.

Thank you for the reply and for your help . I don't have right now a couple of hours to try hard all the pinouts ^^.

PS. Below is a disassembly of the PSS61 GROM opcodes. It's really simple and could be easily changed -- as long as you understand your mapping logic and know what values you want to write to which registers what for.

the main part on my side will be to understand the mapping logic... but I'll give it a try these next days ^^

Let me know if you find something interesting about the GAL