nesdev.com

Apologies if this has been covered before but I couldn't find the answer!

I noticed that some cartridges without MAD-1 decoders have NPN transistors on them, with the base connected to pin 26 on the cartridge connector (through a resistor), the collector to VCC, and emitter to a pulldown resistor and to SRAM CE2 (on games with 64k SRAM or less)

I'm *assuming* this is to somehow prevent glitches in SRAM access during power-ups or power-downs... maybe... or perhaps to reduce power consumption of the battery while the game is on? but I'm not sure what pin 26 does exactly. I've seen a lot of documentation call it /RESET, but that makes it sound like it only changes when the reset button is pressed. Is this correct?

I'm also assuming that tying CE2 high and putting the battery voltage and VCC voltage together with diodes and running that to the SRAM would work just fine. I don't have any examples in front of me to check definitively, but 256k SRAM doesn't have a CE2 pin and therefore probably not a transistor. But this leads me to wonder if the transistor circuit is even necessary? What function does it serve?

Of course I could bust out an oscilloscope and check myself but I thought I'd ask people here if they know first! Thanks!

/RESET is low on power-up, and yes, if you are fiddling with reset button, then it's getting low, too.

NPN transistors are most commonly wired with emitter=GND, are you sure it's really NPN?

With common wiring, transistors do act as inverter, so CE2 would be enabled only during reset, that won't work.

Carts like F-Zero have 24pin SRAMs (16Kbit, without CE2 pin), on that carts the transistor seems to go to /CE.

I haven't checked, but SRAMs with CE2 pin (eg. 64Kbit) might have CE2 wired directly to /RESET (without transistor)?

And yet newer/bigger carts probably have MAD or MM1026/MM1134 chips for battery control.

The same appearance:

With a PNP transistor, that's a common emitter configuration, an inverting amplifier: the difference between Vcc-out is greater than Vcc-in. (Also there's no current limiter: it just looks like a diode from Vcc to /RESET)
With an NPN transistor, that's a common collector configuration, a voltage buffer: out-gnd is always in-gnd minus one diode drop.

The /RESET line inside the SNES is actually bidirectional: The Reset button goes via the CIC, and the CIC tells PPU2 to reset, PPU2 resets PPU1 and also a shared signal which goes everywhere else. There's a series resistor out of PPU2 that goes to the cart slot, which allows the cart to pull it low to reset the S-CPU, S-WRAM, S-SMP, and S-DSP.

To use this transistor to protect the battery-backed save, there needs to be a pull-down resistor on +CE. But /RESET inside the SNES only has a 1kΩ pullup; the pulldown on the cart has to be much weaker than that. Adding a voltage buffer allows a strong pulldown on the cart to protect the save data without loading the /RESET line inside the SNES.

Terrific explanation! I thought it might be a buffer for save protection but I was missing the other side of the circuit inside the SNES.

I guess the question is now, is this completely necessary? How does it really protect the save data?
(I want to use 256k SRAM on a custom board with switchable A14-A11 lines to play games with 256k, 64k, and 16k of SRAM)

You really want to make sure that the RAM stays deselected (in low-power state) when it's not in a powered-up console. Otherwise, at best, it'll draw extra power from the battery and run out faster. (At worst, the other signals may actually cause erroneous writes to RAM). This is easier when you have a +CE input, because you can use a circuit like this one to use /RESET as +POWERGOOD.

For a larger RAM without a +CE input, you can use an external IC to combine /RAMCE and +POWERGOOD into the actual enable for the RAM.

I've also seen a design that used a single transistor to combine the two signals, but I can't find it right now.

Couldn't I just have a pull-up on the /CE pin?

I mean, that's part of it, but what's driving /RAMCE? What happens when it loses power?

If I have a pullup to the SRAM VCC rail, which is supplied by the cartridge VCC pin and battery voltage (through diodes), the battery will keep the rail up after VCC on the cartridge is lost, right?

Here is... I don't know what... it looks a bit out of context... a bot discussing snes cartridges?
https://warosu.org/vr/image/REgX6o9ZhJ30GE2YTcwiWw
Anyways, the schematic on that page shows transistor wiring for SHVC-1A1B-06 carts, that is, without CE2.

You have two inputs (POWERGOOD, whether that's 5V or /RESET) and /RAMCE, and you need an output that's only low when both POWERGOOD is high and /RAMCE is low. As long as you can get that ... it'll work.

There's more than one way to do it. Racermate Challenge (NES) uses a PNP brownout detector and 74HC logic (powered by the combined battery-backed supply) to combine them.

Thanks no cash, I'll check that out when I get home. Also I can provide schematics later once I get home.

I guess what I have is 5V rail from battery and VCC through pullup resistor to /CE pin, which is also connected to decoder output /RAMCE. When /RAMCE from decoder is needed, that drops it to 0. When it's not, its pulled up to 5V. Then when power is off, battery keeps /CE up. Am I explaining myself well?

No, I understand. I just haven't seen anyone try to just use a pullup there, without something providing some isolation, so I'm hesitant to say anything committal.

Here's a schematic that krzysiobal used.

About racermate, using 74xx logic powered by battery... is that good for battery lifetime? Or is it only powering the transistor part from battery?

Looking at https://snescentral.com/system.php pcb photos for chips with CE2...
SHVC-1A3B-01 came up without transistor, but later revisions like SHVC-1A3B-11 do have transistors, supposedly that's been some improvement, either on data protection, or on power consumption.
I don't have schematics for that boards... maybe the older one did use CE2, and the newer one uses /CE instead (same way as on chips without CE2)? I guess pulling /CE high via battery will consume less battery power than pulling CE2 low via battery+inverter.

Anyways, you don't have CE2 on your chip, so you don't need to care about that.

Well only the VCC of the SNES would power the logic, not the battery. That's what the diodes are for.

Thanks everyone for the input. I ordered boards a week ago so when they get in I'll test this out and update with results... assuming the rest of the board was laid out correctly!

Really glad there's still an active community for this kind of stuff. I got into this a bit late haha

Coincidentally, I was looking at this circuit a few weeks ago. That schematic on warosu.org didn't make sense to me, when kevtris saw it he said that can't be right. Sure enough, I took apart my Super Mario World and Mario Paint carts (same board) and it actually is an NPN transistor. That schematic shows PNP, but other than that, it was accurate.

I attached the schematic I'll be trying on NES, but I haven't ordered the board yet. What's funny with mine, is the NVRAM is the only memory. Since NES carts don't have a reset, it'll be a race between the CPU reset and my on-cart reset. That's not exactly safe, but it's just a for-fun project, I'm not expecting to build a bunch of them.