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PostPosted: Tue Nov 23, 2010 12:21 pm 
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Bregalad wrote:
I didn't state the opposite, and that's exactly why tepples fixed is so that it's not REQUIRED to have a large windows. It's required only if you want to compare the pinouts,

No disagreement there. Tepples fixed it well, and I don't have a problem with his fix.
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So I don't know what you're crying about, why you absolutely refuse to enlarge this window.

Stop with the ad hominem comments. They are destructive to cooperation.

Where did I say I refuse to enlarge the window? The original layout required a wider window just to see the content, not even to compare them. It was that which I was objecting to, and calling for a solution that allowed comparison AND didn't require a wider window.

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And if you're that much pissed about my diagrams to be too wide, then you should also be pissed about the toolbar to be on the left when it could be on the top and not take any width.

The toolbar would only be a problem if one wanted the browser window only a couple of inches wide, but that's pretty silly.

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blargg wrote:
Indeed, I merely added the compact one so we could decide the best approach. I do NOT think the individual pinouts should be removed from the Wiki entirely. If one wants the pinout of a PRG ROM, one does not want any other information cluttering it. That may go on a different page that's not specifically comparing pinouts, but it should go somewhere.

The whole point of this thread was to remove duplications of information on the wiki and make info more compact on less pages.

The information shouldn't be made too compact. Duplication has costs, but so combination of information. I don't see a problem with having individual pinouts for the various chips, and a couple of comparison diagrams that merge several pinouts.

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Your way of displaying diagrams is more compact, I'll give you that, so I'd agree to use it on the page. But then the old way should be deleted - it would be crazy to have diagrams in multiple format because people can't agree which one is the "right" one.

That's the issue, there is no one right diagram. The individual pinouts serve different purposes than the comparison ones. I haven't looked closely at your new organization, but to me it would make sense to have pinouts on one page, and another page that gets into comparisons, and the things necessary when using an EPROM in place of a normal ROM. One serves as reference, the other guidance on doing a specific task.

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BTW even your diagrams takes some width, about 2/3 as much as mines.

I'm really not interested in this becoming a battle of whose is better. Yes, the comparison one is wider than a normal pinout, and one comparing say 6 pinouts would be even wider. If you have ideas for comparison pinouts that are even narrower, please share! :)


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PostPosted: Tue Nov 23, 2010 12:23 pm 
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Bregalad wrote:
It's required only if you want to compare the pinouts, and then it really costs you NOTHING (remember that thread about costs ?) to double-click on the main bar of your browser window to temporarly make it full screen to compare them.

I double-click the titlebar, but that only makes my window smaller.

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IEven if you had such as small screen so that an enlarged window can't even show the full thing, most browsers can allow you to resize the page with Ctr + and Ctr - keys.

And a magnifying glass.

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And if you're that much pissed about my diagrams to be too wide, then you should also be pissed about the toolbar to be on the left when it could be on the top and not take any width.

At least that's configurable in Preferences > Skin > Nostalgia. Here's what it looks like.

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Your way of displaying diagrams is more compact, I'll give you that, so I'd agree to use it on the page. But then the old way should be deleted

I'm for deleting the old way too.

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BTW even your diagrams takes some width, about 2/3 as much as mines.

Which is just fine for the critical 960-1024 pixel window widths.


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PostPosted: Tue Nov 23, 2010 12:48 pm 
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Stop with the ad hominem comments. They are destructive to cooperation.

You're right that I (and everyone) should focus on cooperation. I am just feeling that your argument that you need narrow diagrams was biased.
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Where did I say I refuse to enlarge the window?

Well here :
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People who use a 1920x1080 monitor with the "snap" feature of Windows 7 or the "tile vertically" feature of previous Windows versions have a 960px window, which is just a tad narrower than the 1024px of a netbook or a 17" desktop monitor.

and here :
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When I used to have a small monitor, I'd have to do that since there wasn't much room for more than one window, but it was pure tedium, constantly switching between windows. With a larger display, I can put things side-by-side and not constantly switch windows. Web pages which demand a really wide browser window suck, and I don't want the wiki to suck like that. Almost always, information can be presented in a way that doesn't require a really wide page. By doing that, more styles of browsing can be accommodated.


You may not have used the word "refuse", but it was pretty much put that way, as if you couldn't easily enlarge/retract windows in a modern OS.
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The toolbar would only be a problem if one wanted the browser window only a couple of inches wide, but that's pretty silly.

Indeed.
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The information shouldn't be made too compact. Duplication has costs, but so combination of information.

Good point. So now the question is - is multiple-pinouts-in-one diagram such as Blarg's example too compact ?
I think they are ok personally, maybe not as intuitive as the old ones, I'm fine either way. Maybe we need to wait for more opinions before taking a definite decision.

I'm however all against duplicating info on multiple pages, because it does just make things the most confusing IMO.

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Yes, the comparison one is wider than a normal pinout, and one comparing say 6 pinouts would be even wider. If you have ideas for comparison pinouts that are even narrower, please share! :)

Well I'm not the one who said things should be supposed to be narrow.
Also I don't think it could be narrower unless on a 1-dimensional list, which would obviously be worse to read.

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I double-click the titlebar, but that only makes my window smaller.

Interesting. It is linux who does that ? I use it at work and I don't remember it being different from Windows 7. Or maybe I should re-install Linux on my PC to compare what it does ? Anyway this is off topic.

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PostPosted: Tue Nov 23, 2010 1:02 pm 
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Bregalad wrote:
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I double-click the titlebar, but that only makes my window smaller.

Interesting. It is linux who does that ?

In common desktop Linux environments, just as in Windows, double-clicking a window's title bar toggles it between maximized and normal states. The joke was that my Chrome window was already maximized; double-clicking made it "normal" and therefore smaller.


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PostPosted: Sat Nov 27, 2010 6:25 am 
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Well apparently there is noone else who has opinions about it. I guess we should make it all look like Blarg's diagram ?

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PostPosted: Sat Nov 27, 2010 7:33 am 
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One thing I was thinking could be removed are the alternate pins for a particular chip, instead mentioning those in a note below. For example, the EPROM one could mention that A14 also doubles as PGM, and on smaller ones, A15 becomes +5V, and A13 no connection. I tried making a table, but I realized I don't know what the heck that page is describing. Is it telling the pin functions of the chips, or what those pins are wired to on the boards, or both? It states that "For some unknown reasons, unused address lines on smaller ROMs had to be put to +5V". Is this just because those address lines become extra chip select inputs? Also, the pinout suggests that for example pin 20 is a ground line on PRG ROM chips, but is it realls just /CS always selected, with 22 then being an /OE, as with an EPROM?


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PostPosted: Sat Nov 27, 2010 8:52 am 
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As I understand it, "pinout" pages are supposed to describe what each pin does, and how they're wired into a particular board goes in the board family's page.

As for /CS vs. /OE: is there really a difference between the two for mask ROM chips? I was always taught that the difference between /CS and /OE is that /CS must be asserted for a write to complete, and /OE need not.


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PostPosted: Sat Nov 27, 2010 9:19 am 
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tepples wrote:
As I understand it, "pinout" pages are supposed to describe what each pin does, and how they're wired into a particular board goes in the board family's page.

So for EPROM, it tells you what the chip does, but for others it tells you ha mix of what the pin does and how it's wired? That's confusing. It should either show the pinout of the chip, which is a list of the behavior of each pin, OR a pinout of the socket/solder holes, which is a list of what each hole is connected to. For example, pin 20 of a PRG ROM, is it /CS, wired to pin 14 inside the chip, or not connected inside the chip? Is the pinout on the page showing that of the chip or that of the socket?

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As for /CS vs. /OE: is there really a difference between the two for mask ROM chips? I was always taught that the difference between /CS and /OE is that /CS must be asserted for a write to complete, and /OE need not.

Yes; the time from asserting CS to valid data is greater than from asserting OE. I believe it's because when CS is deasserted, the chip goes into a low power mode. Once CS is asserted, the address lines are then used to internally select the byte and get it ready. Then OE just switches from three-state output. Take a look at a 23C020 256Kx8 mask ROM for example, which takes 150ns from CS being asserted, but only 80ns from OE.


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PostPosted: Sat Nov 27, 2010 10:43 am 
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So for EPROM, it tells you what the chip does, but for others it tells you ha mix of what the pin does and how it's wired? That's confusing.

Well, Blargg, I must say you raised a very good question ! You are right that we should definitely make some light on this before editing the page for a final (hopefully better) version.

When I first made the page, by merging multiple diagrams I noticed some were using labels such as "A7" while others using longer labels such as "PRG A7". So I decided to keep the longer labels for EPROM diagrams, so that they indicate not only what the pin is used for, but where it is connected to.
When both are different, for example the /CE pin which is connected to GND, I use GND (/CE).

The problem, is that for Mask ROMs that have pins connected to VCC or GND, you have no way to know if they are unused chip enable signals or not ! The only way would be to mod a board so that the pin is connected to a switch, and change the switch during gameplay. If the game freezes then chances are this was an extra chip enable pin.

I have no idea why Nintendo did multiple boards for multiple PRG sizes.
For example, Bugs Bunny's Carzy Castle, which is 64 KB PRG and 32 KB CHR, uses NES-SBROM, while Dr Mario which is 32 KB PRG and 32 KB CHR, uses NES-SEROM.

The only difference is that A15 becomes VPP, so in theory it would be absolutely no problem to put Dr Mario on a SBROM, A15 would just remain unused and connects to VPP but who cares as VPP is only used during programming. So I have no idea why they had to put it to VCC.

This is even more obscure considering they could have wathever sized CHR-ROMs in the same slots. For example Testis is 32 KB PRG and only 16 KB CHR, but yet they use a SEROM board like Dr Mario which is 32 KB CHR. It doesn't cause them a problem that A14 (PGM) isn't connected to +5V.
However, you know that Nintendo did different boards for NROM-128 and NROM-256 games, which is in the same case : Why couldn't NROM-128 games work on NROM-256 boards with their unused PGM pin connected to A14 ?

Fortunately this stopped at 128 KB and above ROMs, leading to less board per family.


The datasheet you found is interesting, it shows that unused inputs could be asked to be active low or high chip enables. That's what they used in Wizard & Warriors 2 and some other AOROM boards to prevent bus confilcts.

I'm not sure if there is a difference between /CE and /OE. On RAMs of course there is a difference (when writing to it you want /CE low but /OE high). For ROMs if there is a difference, it is in speed and power consumption, but not in functionality. So if it's hard to tell whenever pins connected to +5V or GND on a board are unused enalbe pins, it's even harder to determine which ones are /CE or /OE !

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PostPosted: Sat Nov 27, 2010 11:03 am 
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Bregalad wrote:
For example Testis is 32 KB PRG and only 16 KB CHR

Image
Which of the seven Tetris pieces looks most like a gonad? :P

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I'm not sure if there is a difference between /CE and /OE. On RAMs of course there is a difference (when writing to it you want /CE low but /OE high).

In 6264 datasheets I've seen, /WE overrides /OE, so that it'll still work even if you tie /OE to /CE. The datasheets mention supporting both "8080 style buses" that use /RD and /WR and "6502 style buses" that use /CE and R/W.


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PostPosted: Sat Nov 27, 2010 11:35 am 
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When I first made the page, by merging multiple diagrams I noticed some were using labels such as "A7" while others using longer labels such as "PRG A7". So I decided to keep the longer labels for EPROM diagrams, so that they indicate not only what the pin is used for, but where it is connected to.
When both are different, for example the /CE pin which is connected to GND, I use GND (/CE). The problem, is that for Mask ROMs that have pins connected to VCC or GND, you have no way to know if they are unused chip enable signals or not !

Thanks, this historical explanation makes everything clear, and how things got the current way.

Quote:
I'm not sure if there is a difference between /CE and /OE. On RAMs of course there is a difference (when writing to it you want /CE low but /OE high). For ROMs if there is a difference, it is in speed and power consumption, but not in functionality. So if it's hard to tell whenever pins connected to +5V or GND on a board are unused enalbe pins, it's even harder to determine which ones are /CE or /OE !

Yeah, you can't determine it without testing the actual chip. But access time seems part of functionality, so you can't switch /CS and /OE unless the memory is faster than the usual required. My theory is that 20 is connected to GND so that it can be a /CS, or NC, and work. Same for the upper address line pins being connected to +5V, as CS2, CS3 etc. pins, or NC.

I think it would be good to have a normal ROM pinout compared to the pinouts of the PRG and CHR "sockets" on a board. I believe an EPROM has the same pinout as a ROM when not being used in program mode, so there's little need to even mention PGM, Vpp, etc.

BTW, I like that you're interested in documenting all the board types and why they are that way, because it sheds light on the reasons they are designed that way, and highlights useful approaches to board design. So clarity beyond merely "this board is that way" is good. It makes it easier to remember, for one, since you understand the logic behind the design, rather than it being arbitrary seeming.


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PostPosted: Sat Nov 27, 2010 12:24 pm 
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Well maybe. CNROM has solder pads so that an unused PRGA14 could go to +VCC for a 16 KB PRG game, but yet the only 16 KB PRG CNROM game didn't use that feature.

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Last edited by Bregalad on Sun Nov 28, 2010 4:05 am, edited 1 time in total.

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PostPosted: Sat Nov 27, 2010 4:32 pm 
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Bregalad wrote:
Well maybe. CNROM has solder pads so that an unused PRGA14 could go to +VCC for a 16 KB PRG game, but yet the only 16 KB PRG CNROM game didn't use that feature.

That image page was blank. Bird Week is CNROM, but it's one of the Mapper 185 ones. It took me a while to figure out that you were talking about Joust. It appears BootGod's site doesn't show images unless the Referer is 1. provided and 2. matching.


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PostPosted: Sun Nov 28, 2010 4:06 am 
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OK I fixed it. Yeah just doesn't use that solder pad to put the unused A14 to VCC. This means that particular pin didn't HAVE to be on VCC, at least not for this particular run of mask ROMs.
So the whole point of having different NROM-128 and NROM-256 boards makes no sense to me.

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PostPosted: Sun Nov 28, 2010 6:57 am 
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I figured I'd join in on this discussion...for documenting board details I would think the best way to do it would be like most schematics I've worked with do. At the top level you have chips and named signals between the chips (CPU_A15, for example). Clicking on any chip in the design brings you to that chip's "page" where the chip is the only thing on it. The board-level signal names surround the chip on the wires going into the chip. Inside the chip box you have the chip manufacturer's signal names and pin/ball/land number aligned to the same pins as the signal lines they correspond to. So, if by some esoteric example a board wired CPU_A15 to the PRG ROM's /CE, that would be immediately obvious at the mask ROM level of the schematic.

You could even have a "footprint compatible" selection which would simply interchange the chip's internal details with those of another one to show what the differences were.

Just thoughts.


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