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 Post subject: PHA and PHP issue
PostPosted: Thu Mar 23, 2006 7:19 pm 
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Reading what the "NMOS 65xx Instructions Set" doc says:

Code:
PHA, PHP

        #  address R/W description
       --- ------- --- -----------------------------------------------
        1    PC     R  fetch opcode, increment PC
        2    PC     R  read next instruction byte (and throw it away)
        3  $0100,S  W  push register on stack, decrement S



First PHP/PHA is mostly known as an "implied" instruction while i think its not.It is an "inmediate" one, since as we can see on cycle 2: "read the next instruction byte" and i have made some test to with decoding the byte. Anyway, thats my point of view and doesnt affect nes devlprs or nesem devlprs (i think)

What i dont know how the IC can perform 2 task in only one cycle i mean cycle 1 "fetch xxx, increment xxx" and then cycle 3 too: "Push xxx to stack, decrement xxx"

thanks in advance.

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PostPosted: Thu Mar 23, 2006 7:24 pm 
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All implied addressing instructions (except for BRK) read the byte immediately after the opcode, though they do not increment the program counter.

Also, the 6502 can easily perform multiple tasks per cycle - the program counter and stack pointer are special registers that can be post-incremented on any cycle, and various flags in the status register are frequently updated during other operations. However, of the multiple operations that can occur during a single cycle, only one of these can involve a memory access (for obvious reasons).

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Last edited by Quietust on Thu Mar 23, 2006 7:25 pm, edited 1 time in total.

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PostPosted: Thu Mar 23, 2006 7:24 pm 
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All 6502 instructions fetch at least two instruction bytes; it's a limitation of the underlying microarchitecture. "Implied" means throw away the second byte. "Immediate" means use the second byte's value as the instruction's operand. If the instruction advances the program counter by 1 and not 2, then it's "implied" and not "immediate".


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PostPosted: Thu Mar 23, 2006 7:40 pm 
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ok thanks guys, all clear.

I wanted to know if what im doing is a waste of time, its already done or can be applied another objection that could be done.

Im actually writing a 6502 emulator at "functional level" (well thats how i call it) in c++ i mean oop. So i have classes for the ALU/EU/Registers, etc,all this took me to really decode the opcode (instead of having an array of values/structures that inform addrmode/cycles,etc).
I mean im trying to decode it to have a "6502 opcode format" wich each bit/group of bits says what the IC want to do.. (addr mode, load/store, etc) as i havent found docs about this.
Is there any docs that explain this or someone that have decoded the opcode completly? Please if so where can i find it?

thanks again.

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PostPosted: Fri Mar 24, 2006 4:02 pm 
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Anes wrote:
Is there any docs that explain this or someone that have decoded the opcode completly? Please if so where can i find it?

I think this might be what you are looking for. The 6502 instruction set isn't as "clean" as the RISC machines you design in Comp Arch class, but this seems to be a good explaination of it.
http://axis.llx.com/~nparker/a2/opcodes.html


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PostPosted: Sat Mar 25, 2006 1:58 am 
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teaguecl wrote:
Anes wrote:
Is there any docs that explain this or someone that have decoded the opcode completly? Please if so where can i find it?

I think this might be what you are looking for. The 6502 instruction set isn't as "clean" as the RISC machines you design in Comp Arch class, but this seems to be a good explaination of it.
http://axis.llx.com/~nparker/a2/opcodes.html


But it doesn't give exact timing information.

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PostPosted: Sat Mar 25, 2006 12:31 pm 
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If you want timing information, check out 64doc.

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PostPosted: Sat Mar 25, 2006 12:32 pm 
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But you're right. But it wasn't meant to provide timing information. But it describes how things combine. But it gives insight. BUT BUT BUT (sorry, I've had too much of people's counterpoint-happy style).

It was an interesting document. Good reading for insights into consistency behind the instructions.


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