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PostPosted: Sun Apr 19, 2015 8:59 am 
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hi ... i'm from china ... a pro noob ... my english level not also high .. -_- ...
i just want to ask ... emmm ... for example ... LDA ($F0,X)
lda load 's var addr always at cpu's 2K ram ? ...

ps: my write 's masm pro ... (not write over yet)

.686 ; create 32 bit code
.mmx
.xmm
.model flat, stdcall ; 32 bit memory model
option casemap :none ; case sensitive

NMI_FLAG equ 0x00000001 ;不可屏蔽中断
IRQ_FLAG equ 0x00000002 ;可屏蔽中断

NMI_VECTOR equ 0x0000FFFA ;不可屏蔽中断向量
RES_VECTOR equ 0x0000FFFC ;Reset向量
IRQ_VECTOR equ 0x0000FFFE ;IRQ向量

C_FLAG equ 0x00000001 ; 1: Carry
Z_FLAG equ 0x00000002 ; 1: Zero
I_FLAG equ 0x00000004 ; 1: Irq disabled
D_FLAG equ 0x00000008 ; 1: Decimal mode flag (NES unused)
B_FLAG equ 0x00000010 ; 1: Break
R_FLAG equ 0x00000020 ; 1: Reserved (Always 1)
V_FLAG equ 0x00000040 ; 1: Overflow
N_FLAG equ 0x00000080 ; 1: Negative

STACK_BASE_ADDR equ 0x00000400

public REG_A ; 导出变量符号共外部链接 export var symbols for extern links ...
public REG_X
public REG_Y
public REG_S
public REG_P
public REG_PC
public INT_WARNING
public CPU_MEM_BANK
public NES_2K_RAM

; ml -c /omf masm.asm
.data?

align 4

REG_GROUP dd 6 dup (?) ; 0
INT_WARNING dd ? ; edx + 24
CPU_MEM_BANK dd 8 dup (?)
NES_2K_RAM dd 0x800 dup (?) ; edx + 56

.code
_6502SetAnalysis proc C _opcode : byte, _pCpuSruct : dword

option prologue:none, epilogue:none

REG_A equ [edx]
REG_X equ [edx+4]
REG_Y equ [edx+8]
REG_S equ [edx+12]
REG_P equ [edx+16]
REG_PC equ [edx+20]
INT_WARNING equ [edx+24]
CPU_MEM_BANK_0 equ [edx+28]
CPU_MEM_BANK_7 equ [edx+52]
NES_2K_RAM equ [edx+56]

movzx eax, byte ptr [esp+4]
lea edx, REG_GROUP
jmp AnalysisTable[eax*4]

align 16
AnalysisTable dd SP00, SP01, XX02, SP03, XX04, SP05, SP06, SP07,\
SP08, SP09, SP0A, SP0B, XX0C, SP0D, SP0E, SP0F,\
SP10, SP11, SP12, SP13, SP14, SP15, SP16, SP17,\
SP18, SP19, SP1A, SP1B, SP1C, SP1D, SP1E, SP1F,\
SP20, SP21, SP22, SP23, SP24, SP25, SP26, SP27,\
SP28, SP29, SP2A, SP2B, SP2C, SP2D, SP2E, SP2F,\
SP30, SP31, SP32, SP33, SP34, SP35, SP36, SP37,\
SP38, SP39, SP3A, SP3B, SP3C, SP3D, SP3E, SP3F,\
SP40, SP41, SP42, SP43, SP44, SP45, SP46, SP47,\
SP48, SP49, SP4A, SP4B, SP4C, SP4D, SP4E, SP4F,\
SP50, SP51, SP52, SP53, SP54, SP55, SP56, SP57,\
SP58, SP59, SP5A, SP5B, SP5C, SP5D, SP5E, SP5F,\
SP60, SP61, SP62, SP63, SP64, SP65, SP66, SP67,\
SP68, SP69, SP6A, SP6B, SP6C, SP6D, SP6E, SP6F,\
SP70, SP71, SP72, SP73, SP74, SP75, SP76, SP77,\
SP78, SP79, SP7A, SP7B, SP7C, SP7D, SP7E, SP7F,\
SP80, SP81, SP82, SP83, SP84, SP85, SP86, SP87,\
SP88, SP89, SP8A, SP8B, SP8C, SP8D, SP8E, SP8F,\
SP90, SP91, SP92, SP93, SP94, SP95, SP96, SP97,\
SP98, SP99, SP9A, SP9B, SP9C, SP9D, SP9E, SP9F,\
SPA0, SPA1, SPA2, SPA3, SPA4, SPA5, SPA6, SPA7,\
SPA8, SPA9, SPAA, SPAB, SPAC, SPAD, SPAE, SPAF,\
SPB0, SPB1, SPB2, SPB3, SPB4, SPB5, SPB6, SPB7,\
SPB8, SPB9, SPBA, SPBB, SPBC, SPBD, SPBE, SPBF,\
SPC0, SPC1, SPC2, SPC3, SPC4, SPC5, SPC6, SPC7,\
SPC8, SPC9, SPCA, SPCB, SPCC, SPCD, SPCE, SPCF,\
SPD0, SPD1, SPD2, SPD3, SPD4, SPD5, SPD6, SPD7,\
SPD8, SPD9, SPDA, SPDB, SPDC, SPDD, SPDE, SPDF,\
SPE0, SPE1, SPE2, SPE3, SPE4, SPE5, SPE6, SPE7,\
SPE8, SPE9, SPEA, SPEB, SPEC, SPED, SPEE, SPEF,\
SPF0, SPF1, SPF2, SPF3, SPF4, SPF5, SPF6, SPF7,\
SPF8, SPF9, SPFA, SPFB, SPFC, SPFD, SPFE, SPFF
align 16
ZN_Table dd 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,\
128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128; 80 - FF ... set N flags ... N flags (D7) | 0x80 so = 128
align 16
_6502CycleTable dd 7, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 0, 4, 6, 0,\
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,\
6, 2, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 4, 4, 6, 0,\
2, 2, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,\
6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0,\
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,\
6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0,\
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,\
0, 6, 0, 0, 3, 3, 3, 0, 2, 0, 2, 0, 4, 4, 4, 0,\
2, 6, 0, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0,\
2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0,\
2, 5, 0, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0,\
2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 6, 0,\
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,\
2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 6, 0,\
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0
SP00: ; brk
mov ecx, REG_PC ; - U load pro counter
mov eax, REG_S ; - V load stack
inc ecx ; - U inc counter
sub eax, 12 ; - V brk has 3rd push 3*4
mov [eax+STACK_BASE_ADDR+12], ecx ; - U push pc low bit
mov [eax+STACK_BASE_ADDR+8], ch ; - V push pc high bit
mov ecx, REG_P ; - U load P Reg
mov REG_S, eax ; - V write back REG_S
mov [eax+STACK_BASE_ADDR+4], ecx ; - U push p reg ...
mov ecx, CPU_MEM_BANK_7 ; - V load BANK pointer ...
mov ax, [ecx+1FFEh] ; - U Load IRQ_VECTOR
or REG_P, 0x14 ; - V set I/B flags
mov REG_PC, eax ; - U
mov eax, INT_WARNING ; - V

jmp table ; - N
SP01: ; ora 变址x后间址
mov eax, REG_X ; - U load x reg

mov ecx, REG_PC ; - U
sub eax, 12 ; - V

mov [eax+STACK_BASE_ADDR], ecx ; - U
mov [eax+STACK_BASE_ADDR-4], ecx ; - V

mov ecx, REG_P
mov [eax+STACK_BASE_ADDR-8], ecx ; - V
mov REG_S, eax ;

mov ecx, REG_S ;
mov [ecx + STACK_BASE_ADDR],
sub REG_S, 12 ; - V
and REG_P, B_FLAG ; - V set B flags
mov




_6502SetAnalysis endp
end


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PostPosted: Sun Apr 19, 2015 9:06 am 
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Joined: Fri Nov 12, 2004 2:49 pm
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Location: Chexbres, VD, Switzerland
Hello and welcome.

No, loading for example LDA($F0,X) does not nessesarly load from the CPU's 2k of RAM. It can load from anywhere within the CPU adress space, including RAM but also ROM and memory mapped I/O.
Note that this does not depend on the addressing mode, in 6502's case. There exist other CPUs where some addressing modes can only access a part of the address space for example.

I did not understand the second part of your code. It seems to be PC assembly code, but what is it's purpose ?


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PostPosted: Sun Apr 19, 2015 9:10 am 
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Joined: Mon Jan 03, 2005 10:36 am
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Location: Tampere, Finland
Bregalad wrote:
I did not understand the second part of your code. It seems to be PC assembly code, but what is it's purpose ?

I'm guessing that he's writing an emulator in x86 assembly.

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PostPosted: Sun Apr 19, 2015 5:19 pm 
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Joined: Mon Apr 13, 2015 7:52 am
Posts: 6
Bregalad wrote:
Hello and welcome.

No, loading for example LDA($F0,X) does not nessesarly load from the CPU's 2k of RAM. It can load from anywhere within the CPU adress space, including RAM but also ROM and memory mapped I/O.
Note that this does not depend on the addressing mode, in 6502's case. There exist other CPUs where some addressing modes can only access a part of the address space for example.

I did not understand the second part of your code. It seems to be PC assembly code, but what is it's purpose ?

Thank you for your answer ... ^_^
It seems to be PC assembly code, but what is it's purpose ? <- you are right ... this is x86 asm (masm) ... i want to programming a 6502 's io simulated program code is used to analyze 6502 's opcode :) ... i like asm more than high-level languages (c/c++)


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